CPC

CPC Class H04N

166 patents in CPC class H04N

166 Patents
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Updated 3/25/2026

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A computer apparatus and computer-implemented process for generating a batch record (BR) from a master batch record (MBR) during manufacture of a batch of pharmaceutical product. In the control software, a graphical analysis interface is provided for processing graphs of spectroscopic or chromatographic analysis. A group of fields in the MBR is assigned to the analysis. The operator wears an augmented reality headset and uses this to capture an image of a graph from an instrument display. The graph image is then processed to extract the graph and its metadata, and then further processed to find peaks and assign attribute labels to the peaks, and thus populate the analysis fields. Overlay images are then transmitted to AR headset to present to the operator the populated analysis fields. The operator then accepts or rejects the populated analysis fields by issuing user interface commands.

Augmented reality-based training and troubleshooting is described for medical devices. An electronic mobile device can be equipped with an AR application that, when executed, causes the electronic mobile device to provide augmented reality-based training on how to set up, or perform maintenance on, one or more components of a medical device. The AR application, when executed, can also cause the electronic mobile device to provide augmented reality-based troubleshooting for one or more components of a medical device.

A method and apparatus for measuring a temperature of a substrate located in a semiconductor processing environment is disclosed. The substrate has a top surface and an edge surface, and is positioned in a prescribed location within the semiconductor processing environment. An infrared camera oriented to view one side of the edge surface of the substrate is triggered to obtain an infrared image of the one side of the edge surface of the substrate. The infrared image is processed to obtain a temperature profile of the substrate.

An Artificial Intelligence (AI) multi-frame imaging System on Chip (SoC) incorporates in-pixel embedded analog image processing by performing analog image computation within a multi-frame image pixel. In embodiments, each in-pixel processing element includes a photodetector, photodetector control circuitry with at least three analog sub-frame storage elements, analog circuitry configured to process both neighbor-in-space and neighbor-in-time functions for analog data, and a set of north-east-west-south (NEWS) registers, each register interconnected between a unique pair of neighboring in-pixel processing elements to transfer analog data between the pair of neighboring in-pixel processing elements. In embodiments, the in-pixel embedded analog image processing device takes advantage of high parallelism because each pixel has its own processor, and takes advantage of locality of data because all data is located within a pixel or within a neighboring pixel.

The present technology relates to a light receiving device that includes a pixel array unit in which pixels each having a first tap detecting charge photoelectrically converted by a photoelectric conversion unit and a second tap detecting charge photoelectrically converted by the photoelectric conversion unit are two-dimensionally arranged in a matrix. In the pixel array unit, four vertical signal lines for outputting a detection signal detected by any one of the first tap and the second tap to the outside of the pixel array unit are arranged for one pixel column.

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