CPC

CPC Class H04N

148 patents in CPC class H04N

148 Patents
0 Views
Updated 2/12/2026

Top Patents

A photoelectric conversion apparatus includes a semiconductor substrate including recessed portions and insulators disposed on the respective recessed portions. The semiconductor substrate includes a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region that is of a conductivity type different from the first-conductivity-type and that is formed in the first semiconductor region, a second-conductivity-type third semiconductor region in contact with the second semiconductor region on a surface of the semiconductor substrate, and a first-conductivity-type fourth semiconductor region that includes the recessed portions. The second semiconductor region and the third semiconductor region are surrounded by the fourth semiconductor region on the surface of the semiconductor substrate. The insulators on the recessed portions extend through the fourth semiconductor region and are in contact with the first semiconductor region.

A solid-state imaging device includes a plurality of pixels each including a photoelectric conversion unit, a first holding portion holding charges transferred from the photoelectric conversion unit, a second holding portion holding charges transferred from the first holding portion, and an amplifier unit outputting a signal based on charges in the second holding portion. The photoelectric conversion unit includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region thereunder, a first conductivity type third semiconductor region thereunder, and a second conductivity type fourth semiconductor region thereunder. The first holding portion includes a second conductivity type fifth semiconductor region and a first conductivity type sixth semiconductor region thereunder at a depth of the third semiconductor region being provided. A semiconductor region having a lower potential than the third semiconductor region and the sixth semiconductor region is provided between the third and sixth semiconductor regions.

A semiconductor element includes a semiconductor region (11) of a first conductivity type, a buried charge-generation region (16) of a second conductivity type, buried in an upper portion of the semiconductor region (11) to implement a photodiode (D1) together with the semiconductor region (11) to generate charges, a charge-readout region (15) of the second conductivity type, provided in the semiconductor region (11) to accumulate the charges transferred from the buried charge-generation region (16), and a reset-performing region (12) of the second conductivity type, provided in the semiconductor region (11), a variable voltage is applied to the reset-performing region (12) to change the height of a potential barrier generated in the semiconductor region (11) sandwiched between the charge-readout region (15) and the reset-performing region (12) to exhaust the charges accumulated in the charge-readout region (15). The semiconductor element has a high pixel conversion gain, ultralow noise of a photon counting level and implements a solid-state imaging device.

Explore More Patents

Discover additional patents in the cpc category

Browse All Patents