CPC Class H04N

An array substrate according to an embodiment includes a substrate having a first side and a second side, multiple control lines, multiple data lines, a first region having multiply first interconnect pads, and a second region having multiply second interconnect pads. There is at least one of a distance between the first side and a center line of the first region being longer than a distance between the first side and a center line extending in the first direction of a region including the multiple control lines electrically connected to the multiple first interconnect pads, or a distance between the second side and a center line of the second region being longer than a distance between the second side and a center line extending in the second direction of a region including the multiple data lines electrically connected to the multiple second interconnect pads.

Various embodiments of the present technology may comprise a method and device for a multi-branch transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. At least two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a single photosensitive element or multiple photosensitive elements. The device may comprise a multi-branch channel region defined by the area underlying a gate region and substantially surrounded by the doped regions.

The present technology relates to a solid-state imaging device that can improve the sensitivity of imaging pixels while maintaining AF properties of a focus detecting pixel. The present technology also relates to a method of manufacturing the solid-state imaging device, and an electronic apparatus.The solid-state imaging device includes: a pixel array unit including pixels; first microlenses formed in the respective pixels; a film formed to cover the first microlenses of the respective pixels; and a second microlens formed on the film of the focus detecting pixel among the pixels. The present technology can be applied to CMOS image sensors, for example.