CPC Class G11C

Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

An IC structure includes a first SRAM cell and a second SRAM, where a layout of the second SRAM cell is a mirror image of that of the first SRAM cell about a vertical cell boundary therebetween. The first SRAM cell includes a first PD device and a second PD device disposed over a first fin and a second fin, respectively, where a portion of the first fin and a portion of the second fin corresponding to a channel region of the first and the second PD devices, respectively, each include a first stack of semiconductor layers defined by a channel width W1, a portion of the first fin and a portion of the second fin providing a source terminal of the first and the second PD devices, respectively, are each defined by a width W1′ that is enlarged with respect to the channel width W1.

The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate. The substrate comprises a first well region having a first conductive type. The method also includes forming a first gate structure on the substrate. The method further includes forming a first doped region in the substrate. The first doped region has a second conductive type different from the first conductive type. The first gate structure and the first doped region are included in a first transistor. In addition, the method includes forming a capacitor structure electrically coupled to the first doped region of the substrate. The method also includes forming a second doped region in the substrate. The second doped region has the second conductive type, the second doped region and the first well region collectively serve a diode, and the second doped region is electrically coupled to the first electrode of the capacitor structure and the first doped region.

A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, with the third reference voltage being greater than the high logic voltage of the DRAM cell.

A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.