CPC Class G02F

A display panel including an array substrate and a COF substrate is provided. The COF is provided with a plurality of welded lead lines. The array substrate includes a metal layer disposed on a surface of the substrate, a silicon nitride layer disposed on a surface of the metal layer, and a plurality of terminal wires disposed in a spaced arrangement in a welding region on a surface of the second silicon nitride layer. The welding region between the adjacent terminal wires is provided with through holes, which expose the metal layer. The risk of corrosion and breakage of the welded lead lines on the COF substrate is effectively reduced.

A TFT array substrate includes a pixel region and a wiring region disposed outside the pixel region. The wiring region has a wiring layer including scan or data wirings. A repair wiring layer including repair wiring is disposed insulatedly below or above the wiring layer. A scan or data wiring has a first intersection and a second intersection with a repair wiring section of the repair wiring. When the scan or data wiring is broken, a repair wiring section is cut off the repair wiring by a first cut-off point and a second cut-off point, and the broken scan or data wiring is electrically connected to the repair wiring section through soldering the first intersection and the second intersection. Thus, products that would otherwise be rejected in the manufacturing process of LCD panels can be repaired, which decreases the reject ratio, increases the yield and saves the production cost.

An active device array substrate includes a substrate, first signal lines, second signal lines, pixel units, selection units, an insulating layer, and a driving unit. The second signal lines and the selection lines are electrically connected with the driving unit. The insulating layer is disposed among the first signal lines, the second signal lines and the selection lines and has contact holes. The contact holes are disposed corresponding to the first signal lines, and a portion of the selection lines are electrically connected with the first signal lines via the contact holes. The selection line corresponding to the contact hole the farthest from the driving unit and the closest to a reference axis of the substrate and the selection line corresponding to the contact hole the closest to the driving unit and the reference axis respectively receive a start signal and a terminal signal provided by the driving unit.

A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film. transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.