Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method, comprising: receiving at an interface device a memory request from a processor, the memory request received over a first bus between the processor and the interface device having a first width and operable at a first speed in an interface device; in response to the received memory request, the interface device performing a cache tag look-up routine in multiple memory devices operably coupled to the interface device, and at least one storage device coupled to the interface device; wherein the multiple memory devices are coupled to the interface device through a second bus having a second width wider than the first width of the first bus, and wherein the at least one storage device comprises a flash memory module coupled to a solid-state drive control circuit, wherein the solid-state drive control circuit is coupled to the interface device through a third bus, wherein the third bus is narrower than the second width of the second bus; the cache tag look-up routine determining that only a first portion of the selected information is in one or more of the multiple memory devices memory devices; accessing the multiple memory devices to retrieve the first portion of the selected information and storing the retrieved first portion of the selected information as first information in the interface device; determining that a second portion of the selected information is in the at least one storage device; and accessing at least one storage device to retrieve the second portion of the selected information and storing the retrieved second portion of the selected information as second information in the interface device.
2. The method of claim 1 , wherein the multiple memory devices are stacked relative to one another and are interconnected through vertical conductive channels extending through the multiple stacked memory devices.
This invention relates to a memory system with stacked memory devices interconnected through vertical conductive channels. The system addresses the challenge of increasing memory density and performance in electronic devices by vertically stacking multiple memory devices and connecting them via conductive pathways that extend through the layers. This approach reduces the footprint of the memory system while improving data transfer efficiency between the stacked memory devices. The vertical conductive channels enable direct electrical connections between the layers, eliminating the need for external wiring and reducing signal latency. The stacked configuration allows for higher memory capacity in a compact form factor, making it suitable for applications requiring high-density storage, such as advanced computing systems, solid-state drives, and portable electronics. The vertical interconnections ensure reliable data transmission and minimize interference, enhancing overall system performance. This design overcomes limitations of traditional planar memory architectures by leveraging three-dimensional integration to achieve greater scalability and efficiency.
3. The method of claim 2 , wherein the second bus comprises the vertical conductive channels extending through the multiple memory devices in the stack.
The invention relates to semiconductor memory devices, specifically to a method for forming a three-dimensional memory structure with improved electrical connectivity. The problem addressed is the challenge of efficiently routing electrical signals through multiple stacked memory devices to minimize signal delay and improve performance. The method involves forming a second bus that includes vertical conductive channels extending through the stacked memory devices. These vertical channels provide direct electrical connections between different layers of the memory stack, reducing the need for horizontal interconnects and lowering signal propagation delays. The second bus is integrated with the memory devices during fabrication, ensuring robust and reliable electrical pathways. The vertical conductive channels are strategically positioned to connect critical components within the memory stack, such as memory cells, peripheral circuits, or control logic. By using vertical interconnects, the method reduces the footprint of the memory structure and enhances overall device density. The approach is particularly useful in high-capacity memory systems where efficient signal routing is essential for performance and scalability. The invention improves upon traditional memory architectures by optimizing signal paths and reducing complexity in the interconnect network.
4. The method of claim 1 , further comprising transmitting the first information and the second information to the processor that transmitted the memory request.
A system and method for managing memory access in a computing environment involves processing memory requests from a processor and handling data retrieval or storage operations. The method includes receiving a memory request from a processor, where the request specifies a memory address and an operation type (e.g., read or write). The system then determines whether the requested memory address is within a predefined range. If it is, the system retrieves or stores data from or to a first memory location associated with the address. If the address is outside the predefined range, the system retrieves or stores data from or to a second memory location, which may be a different memory device or a different region of the same memory device. The system then transmits the retrieved data or a confirmation of the storage operation back to the processor that issued the request. Additionally, the system may transmit metadata or status information related to the memory operation, such as error codes, timing data, or other diagnostic information, to the processor. This approach improves memory access efficiency and reliability by dynamically routing requests based on address ranges and providing feedback to the processor.
5. The method of claim 2 , wherein the each of the stacked multiple memory devices is a dynamic random access memory (DRAM) device.
This invention relates to a system for managing multiple stacked memory devices, specifically dynamic random access memory (DRAM) devices, to improve performance and efficiency in data storage and retrieval. The system addresses the challenge of optimizing memory access in high-density memory configurations where multiple DRAM devices are vertically stacked to increase storage capacity while maintaining low latency and high bandwidth. The method involves arranging multiple DRAM devices in a stacked configuration, where each DRAM device operates independently but is synchronized with others to enable efficient data transfer. The system includes a controller that manages data access across the stacked DRAM devices, ensuring that read and write operations are distributed evenly to prevent bottlenecks. The controller also handles error detection and correction, maintaining data integrity across the stacked memory layers. By using DRAM devices in a stacked configuration, the system achieves higher memory density without sacrificing speed, making it suitable for applications requiring large-scale data processing, such as high-performance computing, artificial intelligence, and real-time data analytics. The stacked DRAM architecture reduces the physical footprint of memory modules while increasing storage capacity, which is particularly beneficial in compact electronic devices. The system also includes mechanisms for thermal management to prevent overheating in densely packed memory configurations.
6. The method of claim 5 , wherein the stack of dynamic random access memory (DRAM) devices is further stacked with the interface device, and the stack of DRAM devices is further coupled to the interface device through the vertical conductive channels.
This invention relates to memory systems, specifically the integration of dynamic random access memory (DRAM) devices with an interface device in a stacked configuration. The problem addressed is the need for efficient vertical integration of memory and interface components to improve performance and reduce footprint in electronic systems. The invention describes a method for stacking multiple DRAM devices in a vertical arrangement, where the stack is further integrated with an interface device. The DRAM devices are interconnected through vertical conductive channels, which facilitate high-speed data transfer between the memory layers and the interface. The interface device manages communication between the stacked DRAM modules and external systems, such as processors or controllers. This vertical integration reduces the physical space required while enhancing signal integrity and bandwidth compared to traditional planar or side-by-side configurations. The conductive channels ensure reliable electrical connections across the stacked layers, supporting high-density memory solutions for advanced computing applications. The method enables compact, high-performance memory modules suitable for applications requiring low latency and high throughput, such as data centers, artificial intelligence, and high-performance computing.
7. The method of claim 1 , wherein the at least one storage device comprises at least one solid-state disk (SSD).
This invention relates to data storage systems, specifically addressing the need for efficient and reliable data storage in computing environments. The method involves managing data storage across multiple storage devices, including at least one solid-state disk (SSD). The SSD provides high-speed data access and durability, making it suitable for applications requiring fast read/write operations and frequent data retrieval. The system dynamically allocates data to the SSD based on performance requirements, ensuring optimal use of its high-speed capabilities while balancing wear leveling to extend the SSD's lifespan. The method also integrates the SSD with other storage devices, such as hard disk drives (HDDs), to leverage their respective strengths—SSDs for speed and HDDs for cost-effective, high-capacity storage. By intelligently distributing data across these devices, the system enhances overall storage performance, reduces latency, and improves energy efficiency. The approach is particularly useful in enterprise environments where large datasets must be accessed quickly while maintaining cost-effectiveness. The invention ensures seamless integration of SSDs into existing storage architectures, providing a scalable and adaptable solution for modern data storage needs.
8. The method of claim 1 , wherein the interface device further performs the cache tag lookup routine in a DRAM DIMM coupled to the interface device through a fourth bus, the DRAM DIMM separate from the multiple memory devices coupled to the interface device through the second bus.
This invention relates to a method for optimizing memory access in a computing system by performing cache tag lookups in a dedicated DRAM DIMM (Dual Inline Memory Module) separate from the main memory devices. The system includes an interface device connected to multiple memory devices via a first bus and a second bus, where the second bus is used for data transfers. The interface device also communicates with a dedicated DRAM DIMM through a fourth bus, which is distinct from the buses connecting to the main memory devices. The DRAM DIMM is used to store cache tags, allowing the interface device to perform cache tag lookups efficiently without interfering with the main memory operations. This separation ensures that cache tag lookups do not impact the performance of data transfers between the interface device and the main memory devices. The method improves system efficiency by offloading cache tag management to a dedicated memory module, reducing latency and increasing throughput for memory access operations. The DRAM DIMM is specifically configured to handle cache tag storage and retrieval, ensuring fast and reliable access to cache metadata while maintaining the integrity of the main memory operations. This approach is particularly useful in high-performance computing environments where minimizing memory access latency is critical.
9. The method of claim 2 , wherein the stacked memory devices are operated as cache memory.
The invention relates to memory systems, specifically methods for operating stacked memory devices to improve performance. The problem addressed is the need for faster, more efficient memory access in computing systems, particularly for applications requiring high-speed data retrieval. Traditional memory architectures often suffer from latency and bandwidth limitations, which can bottleneck system performance. The invention involves a method for operating stacked memory devices, where multiple memory layers are vertically integrated to form a high-density, high-bandwidth memory structure. These stacked memory devices are configured to function as cache memory, providing rapid access to frequently used data. By using stacked memory as cache, the system can reduce latency and improve overall processing efficiency. The method includes aligning the stacked memory devices with a processor or memory controller to ensure low-latency communication. Additionally, the stacked memory may be dynamically managed to prioritize critical data, further enhancing performance. This approach leverages the high-density and parallel access capabilities of stacked memory to overcome the limitations of conventional cache architectures. The result is a more responsive and efficient computing system, particularly beneficial for high-performance applications such as data centers, artificial intelligence, and real-time processing.
10. A system, comprising: an interface device configured to couple to a processor through a first high-speed bus, the first bus having a first width; a stack of multiple DRAM memory devices stacked with the interface device and coupled to one another and to the interface device through a second bus having a second width wider than the first width of the first bus; and at least one storage device coupled to the interface device through a third bus; wherein the interface device is configured to, receive a memory request for selected information, perform a cache tag look-up routine in the multiple stacked DRAM memory devices and the at least one storage device, select a device from the storage device and the multiple stacked DRAM memory devices, based on the selected device having the shortest latency for retrieving at least a first portion of the selected information, retrieve and store the selected information, and transmit the information to the processor.
This invention relates to a high-performance memory system designed to reduce latency in data retrieval for processors. The system includes an interface device that connects to a processor via a first high-speed bus with a specific data width. The interface device is integrated with a stack of multiple DRAM memory devices, which are interconnected and coupled to the interface device through a second bus that has a wider data width than the first bus. Additionally, the system includes at least one storage device connected to the interface device via a third bus. The interface device is configured to handle memory requests by performing a cache tag look-up across both the stacked DRAM memory devices and the storage device. Based on this look-up, it selects the device with the shortest latency for retrieving the requested data. The system then retrieves and stores the data, transmitting it to the processor. This approach optimizes data access by dynamically choosing the fastest available storage medium for each request, improving overall system performance. The stacked DRAM configuration enhances memory bandwidth and capacity, while the interface device ensures efficient data routing and retrieval.
11. The system of claim 10 , wherein retrieving and storing the selected information comprises: determining that the selected device contains only a first portion of the selected information; retrieving the first portion of the information from the selected device; and retrieving at least a second portion of the selected information from the storage device.
This invention relates to a system for managing and retrieving distributed information across multiple devices. The problem addressed is the inefficiency and complexity of accessing complete datasets when information is fragmented across different devices, requiring manual or inefficient retrieval processes. The system includes a storage device and multiple devices, each capable of storing portions of information. When a user selects information to retrieve, the system determines whether the selected device contains only a portion of the requested data. If so, the system retrieves the available portion from the selected device and obtains the remaining portions from the storage device. This ensures that the user receives the complete dataset without manual intervention or redundant searches across multiple devices. The system optimizes data retrieval by dynamically identifying and combining fragmented information from different sources, improving efficiency and reducing user effort. The storage device acts as a centralized repository for missing portions, while the selected device provides the locally available data. This approach is particularly useful in environments where data is distributed across multiple devices, such as cloud storage systems, distributed databases, or edge computing networks. The system automates the retrieval process, ensuring seamless access to complete datasets regardless of their physical distribution.
12. The system of claim 10 , wherein the interface device is further operable to store at least one of cache tag values and logical block address (LBA) tables in the stack of multiple DRAM memory devices.
The system relates to memory storage technology, specifically improving data access efficiency in storage systems using multiple DRAM (Dynamic Random-Access Memory) devices. The problem addressed is the latency and inefficiency in accessing frequently used data in storage systems, particularly when dealing with large-scale data operations. Traditional storage systems often rely on slower storage media, leading to bottlenecks in data retrieval and processing. The system includes an interface device connected to a stack of multiple DRAM memory devices. The interface device is configured to manage data storage and retrieval operations across the DRAM devices. A key feature is the ability to store cache tag values and logical block address (LBA) tables within the DRAM stack. Cache tag values help identify which data blocks are stored in the cache, while LBA tables map logical addresses to physical storage locations. By storing these in the DRAM stack, the system reduces the need for external lookups, accelerating data access and reducing latency. The DRAM stack operates as a high-speed cache, allowing for faster retrieval of frequently accessed data compared to traditional storage solutions. This configuration enhances overall system performance, particularly in applications requiring rapid data access, such as databases, virtualization, and high-performance computing. The system optimizes memory usage by leveraging the speed and low-latency characteristics of DRAM, ensuring efficient data management and retrieval.
13. The system of claim 10 , wherein the second bus comprises multiple conductive channels extending vertically from the interface device to each of the stacked DRAM memory devices.
The invention relates to a memory system architecture designed to improve data transfer efficiency between a processing unit and stacked DRAM memory devices. The system addresses the challenge of high-latency and bandwidth limitations in traditional memory architectures by implementing a high-speed interface device that connects to multiple stacked DRAM memory devices. The interface device includes a first bus for communicating with the processing unit and a second bus for interfacing with the stacked DRAM memory devices. The second bus comprises multiple conductive channels that extend vertically from the interface device to each of the stacked DRAM memory devices, enabling parallel data transfer paths. This vertical bus architecture reduces signal propagation delays and increases bandwidth by allowing simultaneous communication with multiple memory layers. The system may also include a controller within the interface device to manage data routing and synchronization between the processing unit and the stacked memory devices. The stacked DRAM memory devices are arranged in a three-dimensional configuration, with each device electrically connected to the interface device through the vertical conductive channels. This design minimizes physical space requirements while enhancing memory access performance. The overall system is optimized for high-speed data processing applications requiring low-latency memory access.
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October 1, 2019
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