Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data processing apparatus comprising: a control bus; and multiple memory units connected by the control bus, each of the multiple memory units comprising a control circuit and a computation circuit, wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar array and a format conversion circuit, the first RRAM crossbar array having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds, and outputs of the comparator circuits are connected to the format conversion circuit; wherein the control circuit is connected to the control bus and configured to: receive a computation instruction for performing a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B; the format conversion circuit being set up to convert the outputs of the comparator circuits into an output corresponding to a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.
The invention relates to a data processing apparatus designed for efficient vector multiplication using resistive random access memory (RRAM) crossbar arrays. The apparatus addresses the challenge of performing fast and energy-efficient matrix and vector operations, which are critical in applications like machine learning and signal processing. The system includes multiple memory units interconnected via a control bus, each unit containing a control circuit and a computation circuit. The computation circuit features an RRAM crossbar array with multiple rows and columns of memory cells, word lines connected to the rows, and comparator circuits linked to each column. The comparators have incremental thresholds to generate voltage signals representing a binary number where the count of '1' bits corresponds to the multiplication result of vectors A and B. The format conversion circuit then converts this binary output into a standard binary number matching the numerical result. The control circuit manages the process by configuring the RRAM cells to represent vector B and setting the word lines according to vector A. This approach leverages RRAM's analog computation capabilities to perform vector multiplication in a single step, reducing latency and power consumption compared to traditional digital methods. The system is particularly suited for high-performance computing tasks requiring rapid matrix operations.
2. The data processing apparatus according to claim 1 , wherein the format conversion circuit comprises: a second RRAM crossbar array connected to receive the outputs of the comparator circuits and configured to generate an output that corresponds to an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and a third RRAM crossbar array connected to receive the output of the second RRAM crossbar array and configured to generate the output corresponding to the second binary number.
This invention relates to data processing apparatus for performing vector multiplication using resistive random-access memory (RRAM) crossbar arrays. The apparatus addresses the challenge of efficiently implementing vector multiplication in hardware, particularly for applications requiring low power consumption and high computational efficiency. The system includes a comparator circuit that receives input vectors A and B, each represented as binary numbers, and generates intermediate signals. These signals are processed by a second RRAM crossbar array to produce an intermediate binary number where the position of a bit set to 1 indicates the numerical result of the multiplication of vectors A and B. The intermediate result is then further processed by a third RRAM crossbar array to generate the final output, which corresponds to a second binary number representing the product of the input vectors. The use of RRAM crossbar arrays enables parallel processing and reduces power consumption compared to traditional digital logic circuits. The apparatus is particularly suited for applications in machine learning, signal processing, and other domains requiring efficient vector operations.
3. The data processing apparatus according to claim 2 , wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows×N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j th word line in the N word lines is a voltage value corresponding to B j , a resistance value of a resistor in the j th row at the first RRAM crossbar array is a resistance value corresponding to A A , B j is the j th element of vector B, A J is the j th element of vector A, and a value of j ranges from 0 to N−1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; and the format conversion circuit receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and generates, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the format conversion circuit, voltage signals corresponding to the second binary number, wherein the second binary number is a binary representation of K.
This invention relates to a data processing apparatus using resistive random-access memory (RRAM) crossbar arrays for performing binary vector multiplication. The apparatus addresses the challenge of efficiently computing dot products of binary vectors in hardware, which is critical for applications like machine learning and digital signal processing. The apparatus includes a first RRAM crossbar array with N rows and N columns of resistors, where each resistor's input is connected to a word line and each column's output is connected to a bit line. The N word lines are controlled by a control circuit, and each bit line is connected to a comparator circuit. The crossbar array generates N current signals on the bit lines based on input voltage signals from the word lines and the resistance values of the resistors. The voltage signals correspond to elements of an N-dimensional binary vector B, while the resistor values correspond to elements of another binary vector A. The comparator circuits convert these current signals into voltage signals, compare them to predefined thresholds, and output a first binary number representing the result of the vector multiplication (A multiplied by B). A format conversion circuit then converts this binary number into a second binary number, which is a binary representation of the scalar result K. The system efficiently performs binary matrix-vector multiplication using RRAM arrays, leveraging resistive states to encode data and analog computation for fast, energy-efficient processing.
4. The data processing apparatus according to claim 3 , wherein the j th comparator circuit in the N comparator circuits comprises a resistor R s of a constant resistance value and a comparator, one end of the resistor R s is connected to the j th bit line in the N bit lines and the comparator, the other end of the resistor R s is grounded, a voltage threshold of the j th comparator circuit is V r *g on *R s *(2j+1)/2, V r indicates a voltage value corresponding to a value 1, and g on indicates a reciprocal of R on .
The invention relates to a data processing apparatus, specifically a comparator circuit used in analog-to-digital conversion (ADC) systems. The problem addressed is the need for precise and efficient voltage comparison in multi-bit ADC architectures, particularly in systems requiring high resolution and low power consumption. The apparatus includes N comparator circuits, each connected to a corresponding bit line in a set of N bit lines. Each comparator circuit (j-th circuit) contains a resistor (R_s) with a fixed resistance value and a comparator. One end of the resistor is connected to the j-th bit line and the comparator, while the other end is grounded. The voltage threshold for the j-th comparator circuit is defined as V_r * g_on * R_s * (2^j + 1)/2, where V_r represents the voltage value corresponding to a binary '1' and g_on is the reciprocal of the on-resistance (R_on) of a switching element. This design ensures that each comparator circuit can accurately compare input voltages against dynamically adjusted thresholds, improving the resolution and accuracy of the ADC. The use of a fixed resistor and a grounded connection simplifies the circuit while maintaining precise voltage reference levels. The threshold calculation incorporates the bit position (j) to enable multi-bit conversion, making the system suitable for high-precision applications. The overall architecture reduces complexity and power consumption compared to traditional ADC designs.
5. The data processing apparatus according to claim 4 , wherein the second RRAM crossbar array comprises a (2N−1) rows×N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−1 word lines, and performs a logic operation according to the voltage signal corresponding to the first computing result and a resistance value of a resistor at the second layer of RRAM crossbar array: O _ 2 , j = { O _ 1 , j + O 1 , j + 1 , j < N - 1 O _ 1 , j , j = N - 1 to obtain voltage signals corresponding to the intermediate binary number, wherein Ō 1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j th bit line of the first RRAM crossbar array, O 1,j+1 is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1) th bit line of the first RRAM crossbar array, and Ō 2,j is a negation of a value corresponding to a voltage signal output by the j th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows×n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.
This invention relates to a data processing apparatus using resistive random-access memory (RRAM) crossbar arrays for binary number operations. The apparatus addresses the challenge of performing efficient logic operations and encoding in binary systems using non-volatile memory arrays. The system includes a first RRAM crossbar array that processes an initial binary number and generates intermediate voltage signals. These signals are fed into a second RRAM crossbar array, structured as a (2N−1) rows by N columns resistor array. Each row's input is connected to a word line, and each column's output is connected to a bit line. The second array performs logic operations based on the input voltage signals and resistor values, producing an intermediate binary number through operations like negation and addition. The output is then processed by a third RRAM crossbar array, structured as an N rows by n columns resistor array, where n is the minimum number of bits needed to represent the integer N. This third array encodes the intermediate binary number into a final binary number based on resistor values and input voltage signals. The system enables efficient binary logic and encoding operations using RRAM arrays, leveraging their resistance states for computation.
6. The data processing apparatus according to claim 5 , wherein the j th word line of the third RRAM crossbar array is connected to the j th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.
This invention relates to resistive random-access memory (RRAM) crossbar arrays used for data processing, particularly in systems requiring efficient memory addressing and data storage. The problem addressed is the need for improved connectivity and encoding within RRAM-based architectures to enhance computational efficiency and reduce hardware complexity. The apparatus includes multiple RRAM crossbar arrays, where the third crossbar array is specifically configured to enable efficient addressing. The jth word line of this third crossbar array is connected to the jth bit line of a second RRAM crossbar array, establishing a direct link between these components. Additionally, the resistance values of resistors in the jth row of the third crossbar array are set to correspond to a binary representation of the integer j+1. This encoding allows for straightforward decoding of row addresses, simplifying the retrieval and storage of data. By integrating these features, the apparatus enables precise and efficient data access, reducing the need for external decoding circuitry and improving overall system performance. The binary resistance encoding ensures that each row can be uniquely identified, facilitating accurate data processing operations. This design is particularly useful in applications requiring high-speed memory access and compact hardware implementations.
7. The data processing apparatus according to claim 1 , wherein vector A is a row vector of a matrix Φ, vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix Φ and a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix Φ and the matrix X.
This invention relates to data processing apparatuses optimized for matrix multiplication operations, particularly in systems requiring high computational efficiency. The apparatus addresses the challenge of performing large-scale matrix multiplications efficiently, which is critical in applications such as machine learning, signal processing, and scientific computing. Traditional matrix multiplication methods often suffer from high latency and power consumption, especially when implemented in hardware. The apparatus includes a memory device storing multiple computation circuits, each configured to perform point multiplication operations between elements of a row vector from a matrix Φ and a column vector from a matrix X. The row vector of Φ and the column vector of X are selected such that the computation circuits collectively execute the full matrix multiplication of Φ and X. The system leverages parallel processing by distributing the multiplication tasks across multiple circuits, significantly reducing computation time. Each computation circuit handles a subset of the multiplications, and the results are combined to produce the final matrix product. This approach minimizes data movement and maximizes hardware utilization, improving energy efficiency and performance. The apparatus is particularly suited for embedded systems, accelerators, or specialized processors where matrix operations are frequent.
8. The data processing apparatus according to claim 1 , wherein the instruction of the processor further comprises a data access instruction, and each memory unit further comprises: a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.
The invention relates to a data processing apparatus designed to improve memory access efficiency in computing systems. The apparatus includes a processor with a computation circuit and multiple memory units, each containing a storage circuit and a control circuit. The control circuit manages data transfer between the computation circuit and the storage circuit. A key feature is the use of a data access instruction that directs the control circuit to read data from or write data to the computation circuit. This allows for controlled and efficient data movement, reducing latency and improving performance. The storage circuit stores data and interfaces with the control circuit, which executes the data access instruction to facilitate seamless data exchange. The overall system enhances processing speed by optimizing memory access operations, particularly in scenarios requiring frequent data transfers between memory and processing units. This design is beneficial for high-performance computing applications where minimizing access delays is critical.
9. A data processing apparatus comprising: a control bus; and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit, wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds; wherein the control circuit is connected to the control bus and configured to: receive a computation instruction for performing a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; and setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.
This invention relates to a data processing apparatus designed for efficient vector multiplication using resistive random access memory (RRAM) technology. The apparatus addresses the challenge of performing fast, energy-efficient matrix and vector operations, which are critical in applications like machine learning and signal processing. The system leverages RRAM crossbar arrays to execute vector multiplication in hardware, reducing latency and power consumption compared to traditional digital processors. The apparatus includes a control bus and a memory unit connected to it. The memory unit contains a control circuit and a computation circuit. The computation circuit features a first RRAM crossbar array with multiple rows and columns of memory cells, word lines connected to each row, and comparator circuits linked to each column. The comparators are configured with incremental thresholds to enable binary output representation. The control circuit receives computation instructions for vector multiplication of vectors A and B. It programs the RRAM crossbar array so that the memory cell states in each column represent elements of vector B. The word lines are then set according to the elements of vector A. The comparator circuits generate voltage signals corresponding to a binary number where the count of '1' bits indicates the numerical result of the vector multiplication. This approach enables efficient, parallel computation of vector products using analog memory operations, improving performance for large-scale data processing tasks.
10. The data processing apparatus according to claim 9 , wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.
This invention relates to a data processing apparatus for performing vector multiplication using resistive random-access memory (RRAM) crossbar arrays. The apparatus addresses the challenge of efficiently implementing vector multiplication in hardware, particularly for applications requiring high-speed, low-power computation such as machine learning and signal processing. The apparatus includes a computation circuit with multiple RRAM crossbar arrays. A first RRAM crossbar array stores vector A, and a second RRAM crossbar array stores vector B. Comparator circuits generate outputs based on comparisons between elements of vectors A and B. These outputs are fed into a second RRAM crossbar array, which converts them into an intermediate binary number where the position of a '1' bit indicates the result of the multiplication of vectors A and B. The intermediate result is then processed by a third RRAM crossbar array, which converts it into a final binary number representing the exact numerical result of the multiplication. The use of RRAM crossbar arrays enables parallel computation, reducing latency and power consumption compared to traditional digital multipliers. The hierarchical arrangement of crossbar arrays allows for efficient binary encoding and decoding of the multiplication result, improving accuracy and computational efficiency. This approach is particularly advantageous for large-scale vector operations in neuromorphic computing and other data-intensive applications.
11. The data processing apparatus according to claim 10 , wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows×N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j th word line in the N word lines is a voltage value corresponding to 4, a resistance value of a resistor in the j th row at the first RRAM crossbar array is a resistance value corresponding to A, 4 is the j th element of vector B, A j is the j th element of vector A, and a value of j ranges from 0 to N−1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and obtain, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the second RRAM crossbar array, voltage signals corresponding to the intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array receives the voltage signals corresponding to the intermediate binary number from the bit lines of second RRAM crossbar array, and convert the intermediate binary number into the second binary number, wherein the second binary number is a binary representation of K.
This invention relates to a data processing apparatus using resistive random-access memory (RRAM) crossbar arrays for performing vector multiplication and binary conversion. The apparatus addresses the challenge of efficiently implementing matrix-vector multiplication and binary encoding in hardware, particularly for applications in machine learning and digital signal processing. The apparatus includes three RRAM crossbar arrays. The first crossbar array performs a dot product operation between two binary vectors, A and B, each of dimension N. The array consists of N×N resistors, where each resistor's row is connected to a word line and each column to a bit line. The control circuit applies voltage signals to the word lines, corresponding to the elements of vector B. The resistance values of the resistors in each row correspond to the elements of vector A. The resulting currents on the bit lines are converted to voltage signals by comparator circuits, which compare these signals against thresholds to generate a binary output vector. The first K elements of this output vector are 1, and the remaining elements are 0, where K is the result of the dot product A·B. The second RRAM crossbar array processes this binary output to produce an intermediate binary number, where the position of the highest 1-bit indicates the value of K. The third RRAM crossbar array then converts this intermediate binary number into a standard binary representation of K. This multi-stage approach enables efficient computation of vector multiplication and binary encoding using resistive memory arrays, leveraging their parallel processing capabilities and non-volatile storage properties.
12. The data processing apparatus according to claim 11 , wherein the j th comparator circuit in the N comparator circuits comprises a resistor R of a constant resistance value and a comparator, one end of the resistor R s is connected to the j th bit line in the N bit lines and the comparator, the other end of the resistor R s is grounded, a voltage threshold of the j th comparator circuit is V r *g on *R s *(2j+1)/2, V r indicates a voltage value corresponding to a value 1, and g on indicates a reciprocal of R on .
This invention relates to a data processing apparatus with comparator circuits for evaluating bit line voltages in a memory system. The apparatus addresses the challenge of accurately determining the state of memory cells by comparing bit line voltages against dynamically adjusted thresholds. Each comparator circuit in the apparatus includes a resistor with a fixed resistance value and a comparator. One end of the resistor is connected to a specific bit line and the comparator, while the other end is grounded. The voltage threshold for the j-th comparator circuit is set to V_r * g_on * R_s * (2^j + 1)/2, where V_r represents the voltage corresponding to a logic value 1, and g_on is the reciprocal of the resistance R_on. This configuration allows for precise voltage comparisons by accounting for variations in bit line resistance and ensuring accurate state detection. The apparatus is designed to improve the reliability of memory read operations by dynamically adjusting comparison thresholds based on the resistance characteristics of the memory cells. The comparator circuits work in conjunction with other components to process and evaluate the voltage levels of the bit lines, enabling efficient and accurate data retrieval.
13. The data processing apparatus according to claim 11 , wherein the second RRAM crossbar array comprises a (2N−1) rows×N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array: O _ 2 , j = { O _ 1 , j + O 1 , j + 1 , j < N - 1 O _ 1 , j , j = N - 1 to obtain voltage signals corresponding to an intermediate binary number, wherein Ō 1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j th bit line of the first RRAM crossbar array, O 1,j+1 a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1) th bit line of the first RRAM crossbar array, and Ō 2,j is a negation of a value corresponding to a voltage signal output by the j th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows×n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.
This invention relates to a data processing apparatus using resistive random access memory (RRAM) crossbar arrays for performing logic operations and encoding binary numbers. The apparatus addresses the challenge of efficiently implementing digital logic and arithmetic operations in hardware using non-volatile memory elements. The system includes a first RRAM crossbar array that performs initial comparisons or logic operations on input voltage signals representing a first binary number. The output of this array is fed into a second RRAM crossbar array, which has a (2N−1) rows by N columns resistor configuration. Each resistor in the second array is connected to a word line at its input and a bit line at its output. The word lines of this array receive voltage signals from the first array's comparator circuits, and the second array performs a logic operation based on these signals and the resistance values of its resistors. The operation combines adjacent bits from the first array, producing an intermediate binary number. The intermediate binary number is then processed by a third RRAM crossbar array, which has an N rows by n columns resistor configuration, where n is at least the number of bits needed to represent the integer N in binary. This array receives the intermediate binary number from the second array's bit lines and encodes it into a second binary number using the resistance values of its resistors. The overall system enables efficient binary logic and arithmetic operations using RRAM-based crossbar arrays, leveraging their non-volatile and reconfigurable properties.
14. The data processing apparatus according to claim 13 , wherein the j th word line of the third RRAM crossbar array is connected to the j th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.
Resistive random-access memory (RRAM) crossbar arrays are used for high-density, non-volatile data storage and processing. A challenge in RRAM-based systems is efficiently implementing arithmetic operations, such as multiplication, while minimizing hardware complexity and power consumption. This invention describes a data processing apparatus that includes multiple RRAM crossbar arrays configured to perform matrix-vector multiplication. The apparatus comprises a first RRAM crossbar array for storing input data, a second RRAM crossbar array for storing weight data, and a third RRAM crossbar array for performing the multiplication operation. The third RRAM crossbar array is structured such that the jth word line is connected to the jth bit line of the second RRAM crossbar array. Additionally, the resistance values of resistors in the jth row of the third RRAM crossbar array correspond to a binary representation of the integer j+1. This configuration enables efficient multiplication by leveraging the inherent properties of RRAM devices, where resistance states represent binary values. The apparatus avoids the need for external multipliers, reducing circuit complexity and improving energy efficiency. The system is particularly useful in neuromorphic computing and in-memory computing applications where low-power, high-speed arithmetic operations are required.
15. The data processing apparatus according to claim 9 , wherein the memory device comprises multiple memory units, each of the multiple memory units comprises a control circuit and a computation circuit, vector A is a row vector of a matrix Φ and vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix Φ and a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix Φ and the matrix X.
This invention relates to a data processing apparatus designed for efficient matrix multiplication, particularly in systems requiring distributed computation across multiple memory units. The apparatus addresses the challenge of performing large-scale matrix multiplications, which are computationally intensive and often bottleneck performance in applications like machine learning, signal processing, and scientific computing. The apparatus includes a memory device with multiple memory units, each containing a control circuit and a computation circuit. These units are configured to perform point multiplication operations between row vectors of a matrix Φ and column vectors of a matrix X. By distributing the computation across multiple units, the system enables parallel processing, significantly accelerating the overall matrix multiplication. Each computation circuit handles a subset of the operations, and the results are combined to produce the final product of Φ and X. This distributed approach reduces latency and improves throughput compared to traditional centralized processing methods. The design is particularly useful in high-performance computing environments where real-time processing of large matrices is required.
16. The data processing apparatus according to claim 9 , wherein the instruction of the processor further comprises a data access instruction, and the memory unit further comprises: a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.
The invention relates to a data processing apparatus designed to improve data handling efficiency in computing systems. The apparatus includes a processor with a computation circuit for performing arithmetic or logical operations and a memory unit for storing and retrieving data. The memory unit contains a storage circuit connected to a control circuit, which manages data flow between the computation circuit and the storage circuit. The processor executes instructions, including data access instructions, to control the transfer of data. When a data access instruction is issued, the control circuit reads data from the computation circuit or writes data into it, facilitating efficient data movement for processing tasks. This design enhances performance by optimizing data access paths and reducing latency in computation-intensive operations. The apparatus is particularly useful in systems requiring high-speed data processing, such as embedded systems, digital signal processing, or general-purpose computing. The invention addresses the challenge of balancing computational speed with memory access efficiency, ensuring seamless data transfer between processing and storage components.
17. A computing device, comprising: a processor configured to send a computation instruction; a memory device connected to the processor, wherein the memory device comprising a control bus and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit; wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds; wherein the control circuit is connected to the control bus and configured to: receive the computation instruction for performing a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.
This invention relates to a computing device with an integrated memory-based computation system, specifically designed for efficient vector multiplication using resistive random access memory (RRAM) technology. The device addresses the challenge of performing fast, energy-efficient vector multiplications, which are fundamental operations in machine learning and signal processing. The computing device includes a processor that sends computation instructions to a memory device. The memory device contains a control bus and a memory unit with a control circuit and a computation circuit. The computation circuit features a first RRAM crossbar array with multiple rows and columns of memory cells, word lines connected to each row, and comparator circuits connected to each column. The comparator circuits are set to incremental thresholds to enable binary output signals. When a vector multiplication instruction is received, the control circuit configures the RRAM crossbar array by setting the memory cells in each column to represent elements of vector B. The word lines are then adjusted according to elements of vector A. The comparator circuits generate voltage signals corresponding to a binary number, where the count of '1' bits in the output represents the numerical result of the multiplication of vectors A and B. This approach leverages the parallel processing capabilities of RRAM to accelerate computations while reducing power consumption.
18. The computing device according to claim 17 , wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar array into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.
The invention relates to a computing device using resistive random-access memory (RRAM) crossbar arrays for efficient vector multiplication. The device addresses the challenge of performing fast and energy-efficient matrix or vector operations, which are critical in applications like machine learning and signal processing. The computing device includes multiple RRAM crossbar arrays organized to perform sequential transformations of input data. A first RRAM crossbar array processes input vectors A and B, generating intermediate results that are compared using comparator circuits. These comparator outputs are fed into a second RRAM crossbar array, which converts them into an intermediate binary number where the position of a '1' bit indicates the multiplication result of vectors A and B. The output of the second RRAM crossbar array is then fed into a third RRAM crossbar array, which further processes the intermediate result to produce a final binary number representing the exact numerical product of vectors A and B. This multi-stage RRAM-based approach enables high-speed, low-power vector multiplication by leveraging the parallel processing capabilities of RRAM arrays and sequential refinement of results through multiple crossbar stages. The system avoids the need for traditional digital multipliers, reducing hardware complexity and energy consumption.
19. The computing device according to claim 18 , wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows x N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j th word line in the N word lines is a voltage value corresponding to B j , a resistance value of a resistor in the j th row at the first RRAM crossbar array is a resistance value corresponding to A j , B j is the j th element of vector B, A j is the j th element of vector A, and a value of j ranges from 0 to N−1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; the second RRAM crossbar array comprises a (2N−1) rows×N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array: O _ 2 , j = { O _ 1 , j + O 1 , j + 1 , j < N - 1 O _ 1 , j , j = N - 1 to obtain voltage signals corresponding to an intermediate binary number, wherein Ō 1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j th bit line of the first RRAM crossbar array, O 1,j+1 is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1) th bit line of the first RRAM crossbar array, and Ō 2,j is a negation of a value corresponding to a voltage signal output by the j th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows×n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.
This invention relates to a computing device using resistive random-access memory (RRAM) crossbar arrays for performing binary vector operations and logic computations. The device addresses the need for efficient hardware implementations of binary arithmetic and logic operations, which are fundamental in digital signal processing, machine learning, and cryptography. The computing device includes three RRAM crossbar arrays. The first array is an N×N resistor matrix where each row is connected to a word line and each column to a bit line. The word lines receive voltage signals representing elements of an N-dimensional binary vector B, while the resistors in each row encode elements of another binary vector A. The resulting currents on the bit lines are converted to voltage signals by comparator circuits, which output a binary number representing the dot product of vectors A and B. The second RRAM crossbar array, a (2N−1)×N resistor matrix, performs a logic operation on the output of the first array, generating an intermediate binary number. The third RRAM crossbar array, an N×n resistor matrix, encodes this intermediate result into a final binary number, where n is the minimum number of bits required to represent the integer N. The device enables efficient binary vector multiplication, logic operations, and encoding in hardware, leveraging the parallel processing capabilities of RRAM crossbar arrays.
20. The computing device according to claim 19 , wherein the j th comparator circuit in the N comparator circuits comprises a resistor R s of a constant resistance value and a comparator, one end of the resistor R s is connected to the j th bit line in the N bit lines and the comparator, the other end of the resistor R s is grounded, a voltage threshold of the j th comparator circuit is V r *g on *R s *(2j+1)/2, V r indicates a voltage value corresponding to a value 1, and g on indicates a reciprocal of R on .
This invention relates to a computing device with a memory array and comparator circuits for reading data. The problem addressed is improving the accuracy and efficiency of data reading in memory systems, particularly in resistive memory arrays where variations in resistance values can affect read operations. The computing device includes a memory array with N bit lines and N word lines, each bit line connected to a corresponding comparator circuit. Each comparator circuit in the N comparator circuits comprises a resistor Rs with a constant resistance value and a comparator. One end of the resistor Rs is connected to the jth bit line and the comparator, while the other end is grounded. The voltage threshold of the jth comparator circuit is determined by the formula Vr * gon * Rs * (2j+1)/2, where Vr represents the voltage value corresponding to a logic value 1, and gon is the reciprocal of Ron, which is the resistance value when a memory cell is in a conductive state. This configuration ensures precise voltage thresholding for accurate data reading, compensating for variations in resistance values within the memory array. The comparator circuits enable reliable detection of stored data by comparing the voltage on each bit line against the dynamically adjusted threshold, improving read accuracy and robustness in memory operations.
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October 29, 2019
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