Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A display device comprising: a display panel; and a power management circuit comprising: a switching regulator for supplying a power to the display panel in a discontinuous conduction mode or in a continuous conduction mode; and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, wherein the switching regulator comprises: a comparator for receiving and monitoring the supplied power; and an RS latch for receiving an output signal from the comparator as a reset signal, and wherein the sensing circuit comprises: a phase lock loop circuit for generating a first clock signal; a phase delay circuit for receiving the first clock signal and generating a second clock signal having a phase delayed from a phase of the first clock signal; a first D flip-flop for receiving an output signal from the RS latch and the first clock signal, and for operating at a rising edge; a second D flip-flop for receiving an output signal from the first D flip-flop and the first clock signal, and for operating at a falling edge; a third D flip-flop for receiving the output signal from the RS latch and the second clock signal, and for operating at a rising edge; a fourth D flip-flop for receiving an output signal from the third D flip-flop and the first clock signal, and for operating at a falling edge; an exclusive OR circuit for receiving an output signal from the second D flip-flop and an output signal from the fourth D flip-flop; a fifth D flip-flop for receiving an output signal from the exclusive OR circuit and a third clock signal having a frequency that is lower than a frequency of the first clock signal; a plurality of registers for sequentially storing signals output from the fifth D flip-flop; and a control circuit for controlling the phase lock loop circuit based on data stored in the registers.
A display device includes a display panel and a power management circuit designed to efficiently regulate power supply. The power management circuit features a switching regulator that operates in either discontinuous conduction mode (DCM) or continuous conduction mode (CCM) to provide power to the display panel. The switching regulator includes a comparator that monitors the supplied power and an RS latch that receives the comparator's output as a reset signal. A sensing circuit detects whether the switching regulator is operating in DCM. This sensing circuit comprises a phase-locked loop (PLL) generating a first clock signal, a phase delay circuit that produces a second clock signal with a delayed phase, and four D flip-flops configured to capture and process signals from the RS latch at different clock edges. The outputs of two of these flip-flops are compared using an exclusive OR (XOR) circuit, whose output is then sampled by a fifth D flip-flop using a slower third clock signal. The results are stored in a series of registers, and a control circuit adjusts the PLL based on the stored data. This system ensures accurate detection of the switching regulator's operating mode, optimizing power efficiency in the display device.
2. The display device of claim 1 , wherein the sensing circuit further comprises a decoder to control the registers.
A display device includes a sensing circuit with a decoder to control registers. The device operates in the field of electronic displays, particularly addressing the challenge of efficiently managing and processing data within display systems. The sensing circuit is designed to monitor and adjust display performance, ensuring accurate color representation and brightness levels. The decoder within the sensing circuit interprets control signals and directs the registers, which store configuration data for display operations. This allows for precise adjustments to display parameters, such as pixel brightness and color calibration, based on real-time feedback. The registers store settings that define how the display processes input signals, ensuring consistent and high-quality visual output. The decoder enables dynamic control over these registers, allowing the display to adapt to varying environmental conditions or user preferences. This system enhances display accuracy and reliability by providing a structured method for managing and updating display configurations. The overall design improves the efficiency and responsiveness of the display device, ensuring optimal performance under different operating conditions.
3. The display device of claim 1 , wherein the RS latch is configured to receive the first clock signal as a set signal.
A display device includes a display panel and a timing controller that generates a first clock signal and a second clock signal. The timing controller provides the first clock signal to a reset-set (RS) latch, which uses the first clock signal as a set signal. The RS latch also receives a reset signal, and its output controls a switching element that adjusts the voltage applied to a pixel circuit in the display panel. The second clock signal is used to drive the switching element, ensuring proper timing for voltage adjustments. The RS latch and switching element work together to stabilize the voltage applied to the pixel circuit, improving display performance by reducing flicker and enhancing image quality. The use of the first clock signal as the set signal for the RS latch ensures precise timing control, allowing the display device to maintain consistent voltage levels across the display panel. This configuration is particularly useful in high-resolution displays where precise timing and voltage control are critical for accurate image rendering.
4. The display device of claim 3 , wherein a frequency of the output signal from the RS latch is equal to the frequency of the first clock signal.
A display device includes a circuit for generating a control signal to drive display elements. The circuit comprises a set-reset (RS) latch that receives a first clock signal and a second clock signal, where the second clock signal has a frequency that is a fraction of the first clock signal's frequency. The RS latch outputs a signal with a frequency equal to the first clock signal, which is used to control the display elements. The circuit also includes a frequency divider that generates the second clock signal by dividing the frequency of the first clock signal. The display device may further include a level shifter to adjust the voltage level of the output signal from the RS latch before it is applied to the display elements. The RS latch ensures that the output signal maintains the same frequency as the first clock signal, enabling precise timing control for the display elements. This design allows for efficient synchronization of display operations with the clock signals, improving display performance and reducing power consumption.
5. The display device of claim 1 , wherein the phase lock loop circuit comprises: a voltage controlled oscillator; a divider for receiving an output signal from the voltage controlled oscillator; a phase frequency detector for receiving an output signal from the divider; a charge pump for receiving an output signal from the phase frequency detector; and a low pass filter for applying only a frequency band of an output signal of the charge pump to the voltage controlled oscillator.
A display device incorporates a phase-locked loop (PLL) circuit to generate precise timing signals for display operations. The PLL circuit includes a voltage-controlled oscillator (VCO) that produces an output signal. This output signal is divided by a divider circuit to adjust the frequency before being fed into a phase-frequency detector. The phase-frequency detector compares the divided signal with a reference signal to detect phase and frequency differences. The detector's output drives a charge pump, which generates a control voltage proportional to the detected phase difference. A low-pass filter then smooths this control voltage, removing high-frequency noise, and applies the filtered signal to the VCO to adjust its oscillation frequency. This closed-loop system ensures the VCO output remains synchronized with the reference signal, providing stable timing for display operations. The PLL circuit's components—VCO, divider, phase-frequency detector, charge pump, and low-pass filter—work together to maintain precise frequency and phase alignment, critical for accurate display synchronization. This design enhances display performance by minimizing timing errors and improving signal integrity.
6. The display device of claim 5 , wherein the control circuit is configured to apply a control signal to the divider.
A display device includes a divider that splits an input signal into multiple output signals, and a control circuit that adjusts the divider's operation. The control circuit generates a control signal to modify the divider's characteristics, such as signal distribution ratios or phase relationships, to optimize display performance. The divider may be a power divider, frequency divider, or signal splitter, depending on the application. The control circuit dynamically adjusts the divider based on operating conditions, such as input signal strength, frequency, or environmental factors, to maintain consistent output quality. This ensures uniform signal distribution across multiple display components, improving image clarity and reducing distortion. The control circuit may also compensate for variations in signal propagation delays or amplitude imbalances introduced by the divider. The display device may be part of a larger system, such as a multi-panel display or a high-resolution imaging system, where precise signal control is critical. The invention addresses challenges in maintaining signal integrity and synchronization in complex display architectures, particularly in applications requiring high precision and reliability.
7. The display device of claim 1 , wherein the control circuit is configured to determine that the switching regulator is operated in the discontinuous conduction mode when each of the registers stores the data having a high value, and is configured to determine that the switching regulator is operated in the continuous conduction mode when each of the registers stores the data having a low value.
A display device includes a switching regulator that supplies power to a display panel and a control circuit that monitors the operating mode of the regulator. The control circuit uses multiple registers to detect whether the regulator is operating in discontinuous conduction mode (DCM) or continuous conduction mode (CCM). When all registers store high-value data, the control circuit determines the regulator is in DCM, where current flow through the inductor is intermittent. When all registers store low-value data, the control circuit determines the regulator is in CCM, where current flow is continuous. The registers capture voltage or current measurements at specific intervals, and their combined state indicates the operating mode. This detection method allows the control circuit to adjust power delivery dynamically, improving efficiency and stability in the display device. The switching regulator may include an inductor, a switching element, and a diode, with the control circuit regulating the switching element to maintain stable output voltage. The display panel may be an organic light-emitting diode (OLED) panel or other type requiring precise power control. The invention addresses the need for accurate mode detection in switching regulators to optimize power efficiency in display applications.
8. The display device of claim 7 , wherein, when the control circuit determines that the switching regulator is operated in the discontinuous conduction mode, the frequency of the first clock signal increases.
A display device includes a switching regulator that converts an input voltage to an output voltage for driving a display panel. The switching regulator operates in different modes, including continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In DCM, the inductor current falls to zero between switching cycles, which can reduce efficiency and increase ripple. To address this, the display device includes a control circuit that monitors the operating mode of the switching regulator. When the control circuit detects that the switching regulator is operating in DCM, it increases the frequency of a first clock signal used to control the switching regulator. Increasing the clock frequency in DCM helps maintain stable operation, reduces ripple, and improves efficiency by minimizing the time the inductor current remains at zero. The control circuit may also adjust other parameters, such as duty cycle or pulse width, to further optimize performance. The display device may include additional features, such as a feedback loop to regulate the output voltage and a driver circuit to control the display panel based on the regulated output voltage. The switching regulator may be a buck converter, boost converter, or buck-boost converter, depending on the voltage conversion requirements. The control circuit dynamically adjusts the clock frequency to ensure efficient and stable power delivery to the display panel.
9. The display device of claim 1 , wherein the control circuit is configured to apply a control signal to the phase delay circuit to control a difference in phase between the first clock signal and the second clock signal.
A display device includes a phase delay circuit that generates a second clock signal by introducing a phase delay into a first clock signal. The phase delay circuit is adjustable to control the phase difference between the two clock signals. A control circuit applies a control signal to the phase delay circuit to dynamically adjust this phase difference. This configuration allows precise synchronization of clock signals in display systems, addressing timing mismatches that can cause visual artifacts such as flicker or distortion. The phase delay circuit may include variable delay elements, such as delay lines or phase shifters, to achieve fine-grained control over the phase relationship. The control circuit monitors system conditions, such as signal propagation delays or environmental factors, and adjusts the phase delay accordingly to maintain optimal synchronization. This technique is particularly useful in high-resolution or high-refresh-rate displays where timing accuracy is critical. The invention improves display performance by reducing timing errors and enhancing image quality.
10. The display device of claim 1 , wherein the output signal of the RS latch has a pulse width that is smaller than a difference in phase between the first clock signal and the second clock signal in the discontinuous conduction mode.
This invention relates to display devices, specifically those using resonant converters in discontinuous conduction mode (DCM) to drive backlight LEDs. The problem addressed is ensuring stable and efficient operation of the display backlight by controlling the pulse width of an RS latch output signal in relation to the phase difference between two clock signals. The RS latch generates an output signal that regulates the switching of the resonant converter. In DCM, the converter operates with discontinuous current, requiring precise timing control to maintain stability and efficiency. The pulse width of the RS latch output signal is adjusted to be smaller than the phase difference between the first and second clock signals, ensuring proper synchronization and preventing overlap that could lead to inefficiencies or instability. The first clock signal may be derived from a system clock or a reference oscillator, while the second clock signal is typically generated based on the resonant converter's operation. The RS latch output signal directly influences the switching frequency and duty cycle of the converter, optimizing power delivery to the LEDs while minimizing losses. This control mechanism enhances the reliability and performance of the display backlight in DCM operation.
11. A power management circuit comprising: a switching regulator for supplying a power to an external device in a discontinuous conduction mode or in a continuous conduction mode; and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, wherein the switching regulator comprises: a comparator for receiving the supplied power to feedback the supplied power; and an RS latch for receiving an output signal from the comparator as a reset signal, and wherein the sensing circuit comprises: a phase lock loop circuit for generating a first clock signal; a phase delay circuit for receiving the first clock signal, and for generating a second clock signal having a phase delayed from a phase of the first clock signal; a first D flip-flop for receiving an output signal from the RS latch and the first clock signal, and operating at a rising edge; a second D flip-flop for receiving an output signal from the first D flip-flop and the first clock signal, and for operating at a falling edge; a third D flip-flop for receiving the output signal from the RS latch and the second clock signal, and for operating at a rising edge; a fourth D flip-flop for receiving an output signal from the third D flip-flop and the first clock signal, and for operating at a falling edge; an exclusive OR circuit for receiving an output signal from the second D flip-flop and an output signal from the fourth D flip-flop; a fifth D flip-flop for receiving an output signal from the exclusive OR circuit and a third clock signal having a frequency that is lower than a frequency of the first clock signal; a plurality of registers for sequentially storing signals output from the fifth D flip-flop; and a control circuit for controlling the phase delay circuit based on data stored in the registers.
A power management circuit is designed to efficiently supply power to an external device in either discontinuous conduction mode (DCM) or continuous conduction mode (CCM). The circuit includes a switching regulator that provides power to the external device and a sensing circuit that detects whether the switching regulator is operating in DCM. The switching regulator features a comparator that receives the supplied power for feedback purposes and an RS latch that receives the comparator's output signal as a reset input. The sensing circuit includes a phase-locked loop (PLL) circuit generating a first clock signal, a phase delay circuit that produces a second clock signal with a delayed phase relative to the first clock signal, and a series of D flip-flops. The first and second D flip-flops process the RS latch's output signal at rising and falling edges of the first clock signal, while the third and fourth D flip-flops process the same signal at rising and falling edges of the second clock signal. An exclusive OR (XOR) circuit compares the outputs of the second and fourth D flip-flops, and a fifth D flip-flop receives the XOR output along with a third clock signal of lower frequency. Multiple registers sequentially store the fifth D flip-flop's output, and a control circuit adjusts the phase delay circuit based on the stored data. This configuration enables precise detection of DCM operation, allowing for optimized power management.
12. The power management circuit of claim 11 , wherein the sensing circuit further comprises a decoder to control the registers.
A power management circuit is designed to efficiently regulate and monitor power distribution in electronic systems. The circuit includes a sensing circuit that detects and measures electrical parameters such as voltage, current, or power consumption. This sensing circuit is enhanced with a decoder that controls multiple registers, allowing for precise configuration and data storage of the sensed parameters. The registers store measurement data, operational states, or control settings, enabling the circuit to dynamically adjust power delivery based on real-time conditions. The decoder interprets control signals or commands to selectively enable, disable, or modify the registers, ensuring accurate and flexible power management. This configuration improves system efficiency, reliability, and responsiveness by providing detailed monitoring and adaptive control over power distribution. The circuit is particularly useful in applications requiring precise power regulation, such as microprocessors, power supplies, or battery management systems. The inclusion of the decoder allows for scalable and programmable control, making the circuit adaptable to various power management scenarios.
13. The power management circuit of claim 11 , wherein the RS latch is configured to receive the first clock signal as a set signal.
A power management circuit is designed to control power distribution in electronic systems, particularly for managing transitions between different power states. The circuit includes a set-reset (RS) latch that receives a first clock signal as a set signal. This configuration ensures that the latch is triggered by the clock signal, enabling precise timing control for power state transitions. The RS latch operates in conjunction with a power control module that generates control signals to activate or deactivate power domains based on system requirements. The latch's set input being driven by the clock signal ensures synchronization with other system operations, preventing power state conflicts and ensuring stable power delivery. This design is particularly useful in low-power electronic devices where efficient power management is critical to extend battery life and maintain system performance. The circuit may also include additional logic to handle reset conditions, ensuring reliable operation during power-up and state transitions. By integrating the clock signal directly into the RS latch, the circuit achieves deterministic power state changes, reducing power consumption and improving system efficiency.
14. The power management circuit of claim 13 , wherein a frequency of the output signal from the RS latch is equal to the frequency of the first clock signal.
A power management circuit is designed to regulate power distribution in electronic systems, particularly for managing transitions between different power states. The circuit includes a set-reset (RS) latch that generates an output signal based on input signals, including a first clock signal. The RS latch ensures that the output signal maintains the same frequency as the first clock signal, enabling precise timing control. This feature is critical for maintaining synchronization in power management operations, such as switching between active and low-power states, where timing accuracy is essential to prevent data corruption or system instability. The circuit may also include additional components, such as a comparator or a logic gate, to process input signals and generate control signals for power regulation. By ensuring the output signal frequency matches the first clock signal, the circuit enhances reliability and efficiency in power management, particularly in systems requiring strict timing constraints. This design is useful in applications like microprocessors, embedded systems, and power-efficient electronic devices where accurate power state transitions are necessary.
15. The power management circuit of claim 11 , wherein the phase lock loop circuit comprises: a voltage controlled oscillator; a divider for receiving an output signal from the voltage controlled oscillator; a phase frequency detector for receiving an output signal from the divider; a charge pump for receiving an output signal from the phase frequency detector; and a low pass filter for applying only a frequency band of an output signal of the charge pump to the voltage controlled oscillator.
A power management circuit includes a phase-locked loop (PLL) circuit designed to stabilize and regulate frequency in electronic systems. The PLL circuit comprises a voltage-controlled oscillator (VCO) that generates an output signal with a frequency proportional to an input voltage. A divider receives the VCO output and scales it down to a lower frequency, which is then compared to a reference signal by a phase-frequency detector. The detector outputs a signal indicating phase and frequency differences, which is processed by a charge pump to generate a control voltage. A low-pass filter smooths this control voltage, removing high-frequency noise before feeding it back to the VCO. This closed-loop system ensures the VCO output maintains a precise, stable frequency aligned with the reference signal. The PLL circuit is integrated into a broader power management system, likely for applications requiring accurate clock synchronization, such as microprocessors, communication devices, or power converters. The design focuses on minimizing phase noise and improving frequency stability, addressing challenges in maintaining consistent performance under varying load conditions.
16. The power management circuit of claim 15 , wherein the control circuit is configured to apply a control signal to the divider.
A power management circuit is designed to regulate power distribution in electronic systems, particularly for managing power delivery to multiple loads with varying requirements. The circuit includes a control circuit that dynamically adjusts power distribution based on system demands, ensuring efficient power usage and preventing overloading. A key component is a divider, which splits power between different loads or operational modes. The control circuit applies a control signal to the divider to modify its operation, allowing precise power allocation. This adjustment can optimize performance, reduce energy waste, or prioritize critical functions during power constraints. The divider may be a voltage divider, current divider, or a switching mechanism that redirects power flow. The control signal can be analog or digital, enabling fine-grained control over power distribution. This feature enhances system reliability and efficiency, particularly in battery-powered or high-performance applications where power management is critical. The circuit may also include feedback mechanisms to monitor power conditions and adjust the divider accordingly, ensuring adaptive power management.
17. The power management circuit of claim 11 , wherein the control circuit is configured to determine that the switching regulator is operated in the discontinuous conduction mode when each of the registers stores the data having a high value, and is configured to determine that the switching regulator is operated in the continuous conduction mode when each of the registers stores the data having a low value.
A power management circuit includes a switching regulator and a control circuit that monitors the operating mode of the regulator. The control circuit determines whether the switching regulator is operating in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) by evaluating data stored in registers. If all registers store data with a high value, the control circuit identifies the regulator as operating in DCM. Conversely, if all registers store data with a low value, the control circuit identifies the regulator as operating in CCM. The registers may be part of a sensing circuit that detects current or voltage conditions in the regulator to determine the conduction mode. The control circuit uses this information to adjust power management strategies, such as switching frequency or duty cycle, to optimize efficiency and performance. The circuit ensures accurate mode detection by relying on multiple registers, reducing the risk of false readings. This approach enhances reliability in power management systems, particularly in applications requiring precise control over switching regulator behavior.
18. The power management circuit of claim 17 , wherein, when the control circuit determines that the switching regulator is operated in the discontinuous conduction mode, the frequency of the first clock signal increases.
A power management circuit includes a switching regulator that operates in different conduction modes, such as continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The circuit monitors the operating mode of the switching regulator and adjusts the frequency of a clock signal based on the detected mode. Specifically, when the switching regulator is operating in discontinuous conduction mode, the frequency of the first clock signal is increased. This adjustment helps optimize the efficiency and performance of the power management circuit by adapting to the varying demands of the switching regulator's operation. The control circuit within the power management circuit determines the operating mode and dynamically adjusts the clock signal frequency accordingly. This ensures that the switching regulator operates efficiently in both continuous and discontinuous conduction modes, improving overall system performance and energy efficiency. The power management circuit may also include additional features such as voltage regulation, current sensing, and protection mechanisms to enhance reliability and functionality. The dynamic frequency adjustment of the clock signal in response to the switching regulator's operating mode is a key aspect of this invention, enabling better power management in electronic devices.
19. The power management circuit of claim 11 , wherein the control circuit is configured to apply a control signal to the phase delay circuit to control a difference in phase between the first clock signal and the second clock signal.
A power management circuit is designed to regulate power distribution in electronic systems, particularly for managing clock signals in integrated circuits. The circuit addresses the challenge of efficiently synchronizing multiple clock signals to optimize power consumption and performance. The circuit includes a phase delay circuit that generates a second clock signal from a first clock signal, with the second clock signal having a controlled phase difference relative to the first. A control circuit applies a control signal to the phase delay circuit to adjust this phase difference, ensuring precise timing alignment between the clock signals. This phase adjustment is critical for applications requiring synchronized operations, such as data processing, signal synchronization, and power management. The control circuit dynamically modifies the phase delay based on system requirements, enabling efficient power distribution and reducing energy waste. The circuit's ability to fine-tune the phase relationship between clock signals enhances system stability and performance while minimizing power losses. This technology is particularly useful in high-performance computing, telecommunications, and other applications where precise clock synchronization is essential.
20. A display device comprising: a display panel; and a power management circuit comprising a switching regulator for supplying a power to the display panel in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, wherein the switching regulator comprises: a comparator for receiving and monitoring the supplied power; and an RS latch for receiving an output signal from the comparator as a reset signal, and wherein the sensing circuit comprises: a phase lock loop circuit for generating a first clock signal; a phase delay circuit for receiving the first clock signal, and for generating a second clock signal having a phase delayed from a phase of the first clock signal; and a determination circuit for receiving the first clock signal, the second clock signal, and an output signal from the RS latch, for outputting a first value when a pulse width of the output signal from the RS latch is smaller than a reference value, and for outputting a second value, which is different from the first value, when the pulse width of the output signal from the RS latch is greater than the reference value.
A display device includes a display panel and a power management circuit designed to efficiently supply power to the display panel. The power management circuit features a switching regulator that operates in either discontinuous conduction mode (DCM) or continuous conduction mode (CCM) to provide power to the display panel. The switching regulator includes a comparator that monitors the supplied power and an RS latch that receives the comparator's output as a reset signal. The power management circuit also includes a sensing circuit that detects whether the switching regulator is operating in DCM. This sensing circuit comprises a phase-locked loop (PLL) circuit that generates a first clock signal, a phase delay circuit that receives the first clock signal and produces a second clock signal with a delayed phase, and a determination circuit. The determination circuit receives the first and second clock signals along with the output signal from the RS latch. It outputs a first value when the pulse width of the RS latch's output signal is smaller than a reference value, indicating DCM operation, and a second value when the pulse width is greater than the reference value, indicating CCM operation. This design allows the display device to dynamically monitor and adjust power delivery modes for improved efficiency and performance.
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May 12, 2020
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