Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device comprising: a first resistive storage element; a second resistive storage element; and logic to couple the first resistive storage element and the second resistive storage element in a series arrangement in a first configuration and to couple the first resistive storage element and the second resistive storage element in a parallel arrangement in a second configuration.
This invention relates to electronic memory devices and addresses the problem of flexible memory configuration. The device includes at least two resistive storage elements. Logic circuitry is provided to control how these resistive storage elements are interconnected. In a first operational configuration, the logic couples the first resistive storage element and the second resistive storage element in series. In a second operational configuration, the same logic couples the first resistive storage element and the second resistive storage element in parallel. This allows for dynamic reconfiguration of the memory array's electrical characteristics, potentially enabling different operating modes or performance optimizations depending on the application. The resistive storage elements themselves are components that store data based on their resistance state, a common characteristic of non-volatile memory technologies.
2. The device of claim 1 , further comprising: a first source line coupled to the first resistive storage element; a first bit line; a first access transistor having a first source/drain coupled to the first bit line and a second source/drain coupled to the first resistive storage element; a second source line coupled to the second resistive storage element; a second bit line; and a second access transistor having a first source/drain coupled to the second bit line and a second source/drain coupled to the first resistive storage element.
This invention relates to a memory device incorporating resistive storage elements, such as those used in resistive random-access memory (ReRAM) or similar non-volatile memory technologies. The device addresses challenges in efficiently reading and writing data by integrating multiple resistive storage elements with access transistors and source/bit lines to enable selective and controlled operation. The device includes at least two resistive storage elements, each coupled to a dedicated source line and a shared bit line through access transistors. The first resistive storage element is connected to a first source line and a first bit line via a first access transistor, where one source/drain terminal of the transistor connects to the bit line and the other connects to the resistive element. Similarly, the second resistive storage element is coupled to a second source line and the same first bit line through a second access transistor, with one source/drain terminal linked to the bit line and the other to the resistive element. This configuration allows independent access to each resistive storage element while sharing a common bit line, improving memory density and reducing complexity. The access transistors act as switches, enabling selective read/write operations by controlling current flow between the bit line and the resistive storage elements. The source lines provide bias voltages or currents to facilitate data storage and retrieval. This architecture enhances scalability and performance in resistive memory arrays by minimizing wiring overhead and ensuring precise control over individual memory cells.
3. The device of claim 2 , further comprising a first word line coupled to gates of the first access transistor and the second access transistor.
A semiconductor memory device includes a memory cell array with multiple memory cells, each having a storage element and a pair of access transistors. The access transistors are coupled to a first word line, which controls their gate terminals. The storage element, such as a capacitor, is connected between the access transistors and a bit line, enabling data storage and retrieval. The first word line activates the access transistors to allow data transfer between the storage element and the bit line. This configuration improves memory cell efficiency and reliability by ensuring synchronized access control. The device may also include additional word lines or control circuitry to manage read and write operations. The invention addresses challenges in high-density memory design, such as minimizing area and power consumption while maintaining fast access times. The use of a shared word line for multiple access transistors simplifies the circuit layout and reduces complexity. This design is particularly useful in dynamic random-access memory (DRAM) and other high-performance memory systems.
4. The device of claim 3 , wherein the logic comprises a storage element memory cell to store a first value to implement the first configuration and a second value to implement the second configuration.
The invention relates to a configurable electronic device, specifically a logic circuit that can be dynamically reconfigured between at least two different operational states. The problem addressed is the need for flexible hardware that can adapt its functionality without requiring physical modifications or extensive reconfiguration overhead. The device includes a logic circuit that can be switched between a first configuration and a second configuration based on stored configuration values. The logic circuit is designed to perform different operations or functions depending on the active configuration. To enable this reconfiguration, the device incorporates a storage element, such as a memory cell, which stores a first value corresponding to the first configuration and a second value corresponding to the second configuration. The stored values determine the operational state of the logic circuit, allowing it to switch between configurations as needed. This approach reduces the need for dedicated hardware for each function, improving efficiency and adaptability in electronic systems. The storage element ensures that the configuration values are retained, enabling reliable switching between states. The invention is particularly useful in applications requiring dynamic reconfiguration, such as programmable logic devices, adaptive computing systems, or hardware acceleration modules.
5. The device of claim 4 , further comprising a second word line coupled to the storage element.
A non-volatile memory device includes a storage element configured to store data and a first word line coupled to the storage element to control access to the stored data. The device further includes a second word line also coupled to the storage element, allowing for additional control over data access or storage operations. The second word line may enable independent or coordinated control of different aspects of the storage element, such as selective activation, data retention, or multi-level programming. This dual-word-line configuration enhances flexibility in memory operations, improving performance, reliability, or storage density. The storage element may be a floating-gate transistor, charge-trap cell, or other non-volatile memory structure, where the second word line provides supplementary control beyond what the first word line alone can achieve. The device may be part of a larger memory array, where multiple storage elements share word lines to optimize layout and reduce interconnect complexity. The second word line may also facilitate advanced features like multi-bit storage, reduced power consumption, or improved endurance by enabling finer control over the storage element's electrical characteristics.
6. The device of claim 4 , wherein the logic comprises: a first routing transistor having a first source/drain coupled to the first resistive storage element, a second source/drain coupled to the first source line, and a gate coupled to the storage element; and a second routing transistor having a first source/drain coupled to the second resistive storage element, a second source/drain coupled to the second source line, and a gate coupled to the storage element.
This invention relates to a memory device incorporating resistive storage elements and routing transistors for selective data access. The device addresses challenges in efficiently managing data storage and retrieval in memory arrays, particularly in resistive memory technologies where precise control of current paths is critical. The device includes a storage element and at least two resistive storage elements. A first routing transistor is connected between the first resistive storage element and a first source line, with its gate controlled by the storage element. Similarly, a second routing transistor connects the second resistive storage element to a second source line, also gated by the storage element. This configuration allows the storage element to selectively enable or disable current flow through the resistive storage elements, facilitating controlled read/write operations. The routing transistors act as switches, ensuring that only the intended resistive storage element is accessed during memory operations. The storage element, which may be a separate memory cell or a control circuit, determines the state of the routing transistors, thereby directing current paths and preventing unintended interactions between adjacent memory cells. This selective routing improves data integrity and reduces power consumption by minimizing unnecessary current flow. The invention is particularly useful in high-density memory arrays where minimizing cross-talk and optimizing access speed are critical. By integrating routing transistors with resistive storage elements, the device enhances the reliability and efficiency of memory operations in advanced semiconductor storage systems.
7. The device of claim 6 , wherein the storage element comprises a memory cell having a first node and a second node storing a complement of the first node, the gate of the first routing transistor is coupled to the first node, and the gate of the second routing transistor is coupled to the second node.
This invention relates to memory devices, specifically a storage element with improved routing control. The problem addressed is the need for efficient and reliable data routing in memory circuits, particularly in systems requiring complementary data storage and retrieval. The device includes a storage element with a memory cell that stores data as complementary values on two nodes. The first node holds a primary data value, while the second node holds its complement. The storage element also includes two routing transistors, each with a gate terminal. The gate of the first routing transistor is connected to the first node, and the gate of the second routing transistor is connected to the second node. This configuration ensures that the routing transistors are controlled directly by the stored data values, enabling precise and synchronized data routing based on the complementary signals. The routing transistors selectively pass or block data signals depending on the state of the memory cell, improving data integrity and reducing routing errors. This design is particularly useful in memory architectures where complementary data storage is required, such as in static random-access memory (SRAM) or other volatile memory systems. The direct coupling of the routing transistor gates to the memory cell nodes ensures fast and reliable switching, enhancing overall system performance.
8. The device of claim 7 , wherein the first routing transistor comprises an N-type transistor, and the second access transistor comprises a P-type transistor.
This invention relates to semiconductor memory devices, specifically dynamic random-access memory (DRAM) with improved data retention and access efficiency. The problem addressed is the trade-off between data retention time and fast access speeds in conventional DRAM cells, which often use identical transistor types for both routing and access functions. The device includes a memory cell with a storage capacitor and two transistors: a first routing transistor and a second access transistor. The routing transistor controls data flow between the memory cell and a bitline, while the access transistor enables or disables the routing transistor based on a wordline signal. The key innovation is the use of complementary transistor types for these functions: the routing transistor is an N-type transistor (e.g., NMOS), and the access transistor is a P-type transistor (e.g., PMOS). This configuration improves data retention by reducing leakage current through the routing transistor while maintaining fast access times by leveraging the P-type transistor's characteristics. The complementary transistor types also enhance noise immunity and reduce power consumption during standby modes. The device may be integrated into larger memory arrays with multiple cells, each following this structure to achieve uniform performance across the memory chip.
9. The device of claim 7 , wherein the memory cell comprises a static random access memory cell.
A semiconductor memory device includes an array of memory cells, each configured to store data. The memory cells are arranged in rows and columns, with each cell connected to a word line and a bit line. The device further includes a control circuit that selectively activates the word lines to access the memory cells for read or write operations. The memory cells are static random access memory (SRAM) cells, which retain data as long as power is supplied. SRAM cells use bistable latching circuitry, typically composed of cross-coupled inverters, to store a single bit of data. The control circuit manages the timing and voltage levels applied to the word lines and bit lines to ensure reliable data storage and retrieval. The SRAM cells may be organized in a multi-port configuration, allowing simultaneous read and write operations. The device may also include error correction circuitry to detect and correct data errors during operation. The overall design optimizes power efficiency, speed, and reliability for high-performance computing applications.
10. The device of claim 2 , further comprising peripheral circuitry to combine current on the first source line with current on the second bit line.
A memory device includes a memory array with a plurality of memory cells arranged in rows and columns. Each memory cell is connected to a first source line and a second bit line. The device further includes peripheral circuitry that combines the current flowing through the first source line with the current flowing through the second bit line. This combination of currents is used to determine the state of the memory cell, such as whether it is in a programmed or erased state. The peripheral circuitry may include current sensing or amplification components to accurately measure the combined current. The memory array may be a non-volatile memory, such as flash memory, where the memory cells store data by trapping charge in a floating gate or charge-trapping layer. The combined current measurement improves read accuracy by reducing noise and interference from adjacent cells or lines. The device may also include additional circuitry to control the voltage levels applied to the source and bit lines during read operations. The peripheral circuitry ensures reliable data retrieval by processing the combined current signals to distinguish between different memory states.
11. A device comprising: a memory cell; a first resistive storage element; a second resistive storage element; a first source line; a second source line; a first routing transistor having a first source/drain coupled to the first resistive storage element, a second source/drain coupled to the first source line, and a gate coupled to the memory cell; and a second routing transistor having a first source/drain coupled to the second resistive storage element, a second source/drain coupled to the second source line, and a gate coupled to the memory cell.
This invention relates to a memory device architecture that uses resistive storage elements and routing transistors controlled by a memory cell. The device addresses challenges in memory systems where efficient data routing and storage are required, particularly in applications needing high-density or non-volatile storage solutions. The device includes a memory cell that controls two routing transistors, each connected to a resistive storage element. The first routing transistor couples a first resistive storage element to a first source line, while the second routing transistor couples a second resistive storage element to a second source line. Both routing transistors are gated by the memory cell, enabling selective activation of the resistive storage elements. The resistive storage elements store data based on their resistance states, which can be read or written through the source lines when the corresponding routing transistor is activated. This configuration allows for flexible data routing and storage, improving memory efficiency and scalability. The memory cell acts as a control mechanism, determining whether the resistive storage elements are accessible via their respective source lines. This design is useful in memory systems requiring dynamic reconfiguration or multi-level storage capabilities.
12. The device of claim 11 , further comprising; a first bit line; a second bit line; a first access transistor having a first source/drain coupled to the first bit line and a second source/drain coupled to the first resistive storage element; and a second access transistor having a first source/drain coupled to the second bit line and a second source/drain coupled to the first resistive storage element.
This invention relates to memory devices, specifically resistive memory cells with improved access transistor configurations. The problem addressed is enhancing data read/write operations in resistive memory by optimizing the connection between resistive storage elements and bit lines. The device includes a resistive storage element, such as a resistive random-access memory (ReRAM) cell, which stores data based on its resistance state. To enable selective access, the device incorporates a first bit line and a second bit line, each connected to the resistive storage element through separate access transistors. The first access transistor has one source/drain terminal connected to the first bit line and the other terminal connected to the resistive storage element. Similarly, the second access transistor has one source/drain terminal connected to the second bit line and the other terminal also connected to the resistive storage element. This dual-transistor configuration allows independent control of read and write operations, improving reliability and reducing interference between adjacent memory cells. The access transistors may be field-effect transistors (FETs) or other suitable switching devices, ensuring efficient current flow during programming and sensing operations. The overall design aims to enhance performance, scalability, and integration density in resistive memory architectures.
13. The device of claim 12 , wherein the memory cell comprises a first node and a second node storing a complement of the first node.
A non-volatile memory device includes a memory cell with a first node and a second node that stores a complement of the first node. The memory cell is configured to store data in a differential manner, where the first node holds a data bit and the second node holds its logical inverse. This complementary storage improves data integrity and reliability by allowing error detection and correction through comparison between the two nodes. The memory cell may be part of a larger memory array, where each cell is individually addressable for read and write operations. The device may also include peripheral circuitry for managing data access, such as sense amplifiers to detect stored values and write drivers to program the cells. The complementary storage scheme is particularly useful in non-volatile memory technologies like flash memory, where charge retention and read disturbances can affect data accuracy. By storing both a data bit and its complement, the device can mitigate errors caused by charge leakage or read disturbances, ensuring more reliable data retrieval. The memory cell may be implemented using various non-volatile memory technologies, including floating-gate transistors, charge-trap memory, or resistive memory, depending on the specific application requirements. The complementary storage approach enhances fault tolerance and extends the operational lifespan of the memory device.
14. The device of claim 12 , wherein the first routing transistor comprises an N-type transistor, and the second access transistor comprises a P-type transistor.
This invention relates to semiconductor memory devices, specifically dynamic random-access memory (DRAM) cells with improved data retention and access performance. The problem addressed is the trade-off between data retention time and access speed in conventional DRAM cells, where N-type access transistors are typically used for both read and write operations, leading to charge leakage and reduced retention time. The invention describes a DRAM cell architecture that uses a first routing transistor as an N-type transistor and a second access transistor as a P-type transistor. The N-type routing transistor is connected to a bitline and controls data transfer between the bitline and a storage node, while the P-type access transistor is connected to a wordline and controls access to the storage node. This combination improves data retention by reducing leakage current during standby mode while maintaining fast access speeds during read/write operations. The P-type access transistor minimizes subthreshold leakage, enhancing retention time, while the N-type routing transistor ensures efficient data transfer during active operations. The invention also includes a capacitor for storing charge and a sense amplifier for detecting stored data, forming a complete memory cell structure. This configuration balances retention time and access performance, making it suitable for high-density memory applications.
15. The device of claim 12 , wherein the memory cell comprises a static random access memory cell.
This neuromorphic memory device incorporates two resistive storage elements (a first and a second). Its configuration is managed by a dedicated control memory cell, which, in this specific instance, is a Static Random Access Memory (SRAM) cell. This SRAM cell stores a value that dictates how the device's electrical paths are established. The device includes a first and a second source line. Two routing transistors are used: a first routing transistor connects the first resistive storage element to the first source line, and a second routing transistor connects the second resistive storage element to the second source line. Both routing transistors are controlled by the SRAM cell, meaning its stored configuration value determines their operational state. For accessing data, the device provides a first bit line and a second bit line, each associated with an access transistor. The first access transistor connects the first bit line to the first resistive storage element. The second access transistor connects the second bit line to the *first* resistive storage element. This setup allows the two resistive storage elements to be dynamically coupled in either a series or parallel arrangement, enabling different resistance states based on the configuration stored in the SRAM control cell. ERROR (embedding): Error: Failed to save embedding: Could not find the 'embedding' column of 'patent_claims' in the schema cache
16. The device of claim 11 , further comprising peripheral circuitry to combine current on the first source line with current on the second bit line.
A memory device includes a memory cell array with multiple memory cells arranged in rows and columns. Each memory cell is connected to a first source line and a second bit line. The device further includes peripheral circuitry designed to combine the current flowing through the first source line with the current flowing through the second bit line. This combination of currents allows for enhanced readout accuracy and improved sensing of the memory cell's state. The peripheral circuitry may include current mirrors, amplifiers, or other analog components to merge the two currents and generate a combined signal for further processing. The memory cells may be non-volatile, such as resistive RAM (ReRAM) or phase-change RAM (PCRAM), where the combined current readout helps distinguish between different resistance states. The device may also include additional circuitry for addressing, programming, and erasing the memory cells, ensuring reliable data storage and retrieval. The combined current readout technique improves signal-to-noise ratio and reduces errors in memory read operations.
17. A method, comprising: coupling a first resistive storage element to a second resistive storage element in a memory cell to a selected one of a series arrangement in a first configuration or a parallel configuration in a second configuration, wherein the memory cell has a plurality of resistance states based on data stored in the first resistive storage element and the second resistive storage element and the selected first configuration or second configuration; and reading the memory cell to generate a current related to a particular resistance state of the plurality of resistance states.
This invention relates to resistive memory technology, specifically addressing the challenge of increasing data storage density and reliability in memory cells. The method involves a memory cell containing two resistive storage elements that can be selectively coupled either in series or in parallel, depending on the desired configuration. In the series arrangement (first configuration), the combined resistance of the two elements is the sum of their individual resistances, while in the parallel arrangement (second configuration), the combined resistance is lower than either element alone. The memory cell leverages these configurations to achieve multiple resistance states, each representing different data values. By switching between series and parallel coupling, the memory cell can store more data states than either element could alone, improving storage density. The method also includes reading the memory cell to measure the resulting current, which corresponds to a specific resistance state, thereby enabling data retrieval. This approach enhances memory performance by increasing the number of distinguishable states per cell while maintaining reliability. The invention is particularly useful in non-volatile memory applications where high-density storage and efficient data access are critical.
18. The method of claim 17 , wherein the plurality of resistance states comprises between six and eight resistance states.
This invention relates to a method for operating a memory device that utilizes a plurality of resistance states to store data. The method addresses the challenge of increasing data storage density and reliability in resistive memory technologies, such as resistive random-access memory (ReRAM), phase-change memory (PCM), or similar non-volatile memory systems. By employing multiple resistance states, the memory device can store more than one bit of data per cell, improving storage efficiency. The method involves programming a memory cell to one of a plurality of distinct resistance states, where the number of states is between six and eight. Each resistance state represents a unique data value, allowing for multi-level cell (MLC) storage. The method includes applying specific voltage or current pulses to the memory cell to transition between these resistance states, ensuring precise and stable switching. Additionally, the method may involve reading the resistance state of the memory cell by measuring its electrical resistance and comparing it to predefined reference levels corresponding to each of the six to eight states. The invention also includes techniques for error correction and state retention, ensuring long-term reliability. By using intermediate resistance states, the memory device achieves higher storage density compared to binary (two-state) memory cells while maintaining acceptable read/write performance and endurance. This approach is particularly useful in applications requiring compact, high-capacity storage solutions, such as embedded memory, solid-state drives, and neuromorphic computing systems.
19. The method of claim 17 , wherein coupling the first resistive storage element to the second resistive storage element comprises configuring a storage element to store a first value corresponding to the first configuration and to have a second value corresponding to the second configuration.
This invention relates to resistive storage elements, specifically methods for coupling two such elements to enable configurable storage states. Resistive storage elements, such as memristors or ReRAM devices, are used in non-volatile memory and neuromorphic computing applications. A key challenge is efficiently managing multiple configurations of these elements to represent different data states. The invention addresses this by providing a method to couple a first resistive storage element to a second resistive storage element, where the coupling is achieved by configuring a storage element to store a first value corresponding to a first configuration and a second value corresponding to a second configuration. This allows the system to dynamically switch between configurations, enabling flexible data representation. The storage element can be part of a larger array or circuit, where the first and second configurations may represent different resistance states, logic states, or memory states. The method ensures that the coupling process is reversible and programmable, allowing for dynamic reconfiguration of the storage elements. This approach improves the versatility of resistive storage systems, making them suitable for advanced computing and memory applications.
20. The method of claim 19 , further comprising controlling a first routing transistor coupled to the first resistive storage element and a second routing transistor coupled to the second resistive storage element based on the first value or the second value stored in the storage element.
This invention relates to memory systems, specifically resistive memory arrays, addressing challenges in data routing and access control. The method involves a memory system with at least two resistive storage elements, each capable of storing a first or second value. A storage element holds a configuration value that determines the routing path for data within the array. The method further includes controlling routing transistors connected to each resistive storage element based on the stored value. The routing transistors selectively enable or disable data paths to the storage elements, ensuring proper data flow and preventing conflicts. This control mechanism optimizes data access efficiency and reliability in resistive memory arrays by dynamically adjusting routing based on stored configuration values. The system may include additional circuitry to manage the routing transistors, ensuring accurate and timely switching operations. The invention improves memory performance by reducing access latency and enhancing data integrity in resistive memory architectures.
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June 2, 2020
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