Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A circuit, comprising: a flip-flop having an input configured to receive an input signal, a clock input configured to receive a wake-up signal, a reset input, and a data output; a shutdown circuit including a logic circuit configured to logically combine a signal generated at the data output of the flip-flop with a first control signal indicating that a voltage of a power supply is sufficient; and a power management reset circuit having an input configured to receive a second control signal output by the logic circuit, the power management reset circuit configured to generate a reset signal in response to the second control signal; wherein the reset signal is further applied to the reset input of the flip-flop.
This circuit manages system state transitions, especially for power-saving modes. It includes a flip-flop that receives an input signal and a wake-up signal, and outputs a data signal. A shutdown circuit contains logic that combines this flip-flop's data output with a first control signal, which indicates that the power supply voltage is sufficient. The result of this combination (a second control signal) then triggers a power management reset circuit. This power management reset circuit generates a system reset signal, which is also fed back to reset the flip-flop itself, ensuring controlled state transitions and proper initialization.
2. The circuit of claim 1 , further comprising a microcontroller core having a reset controlled by the reset signal.
This circuit is designed for power and reset management within a microcontroller system. It features a flip-flop that receives an input signal and a wake-up signal, with its output feeding into a shutdown circuit. The shutdown circuit's logic combines the flip-flop's output with a signal indicating a stable power supply. This combined signal then activates a power management reset circuit, which generates a system reset signal. This crucial reset signal controls the reset of an attached microcontroller core, ensuring proper initialization, and also resets the flip-flop itself, so the entire system can start in a known state upon waking.
3. The circuit of claim 2 , wherein the microcontroller core and power management reset circuit are not active in a stand-by mode of operation in order to save power and wherein the wake-up signal is asserted to wake the microcontroller core from the stand-by mode of operation.
This power management circuit for a microcontroller system incorporates a flip-flop, a shutdown circuit, a power management reset circuit, and a microcontroller core. The flip-flop receives an input and a wake-up signal, and its output is logically combined with a power supply sufficiency signal within the shutdown circuit. This combined signal triggers the power management reset circuit to generate a reset signal for the microcontroller core and the flip-flop. To conserve power, both the microcontroller core and the power management reset circuit are inactive in a stand-by mode. The wake-up signal is then asserted to wake the microcontroller core from this stand-by mode, initiating the power-up and reset sequence.
4. The circuit of claim 3 , wherein the flip-flop and shutdown circuit remain active during the stand-by mode of operation.
This power-managing circuit integrates a flip-flop, a shutdown circuit, a power management reset circuit, and a microcontroller core. The flip-flop processes an input and a wake-up signal, its output is logically combined with a power supply sufficiency signal in the shutdown circuit. This combined signal triggers the power management reset circuit to generate a reset signal for the microcontroller core and the flip-flop. For power efficiency, the microcontroller core and the power management reset circuit are inactive during stand-by mode, with the wake-up signal initiating their return to activity. Crucially, the flip-flop and the shutdown circuit remain active even during stand-by, allowing them to monitor for the wake-up signal and initiate the power-up sequence.
5. The circuit of claim 3 , wherein the microcontroller core, the flip-flop, shutdown circuit and power management reset circuit are components of a microcontroller circuit.
This circuit provides robust power and reset management for a microcontroller system. It includes a flip-flop, a shutdown circuit (whose logic combines the flip-flop's output with a power supply sufficiency signal), and a power management reset circuit that generates a reset signal for a microcontroller core and the flip-flop. During stand-by mode, to conserve power, the microcontroller core and power management reset circuit are inactive, becoming active only upon assertion of a wake-up signal. All these elements—the microcontroller core, the flip-flop, the shutdown circuit, and the power management reset circuit—are integrated as key components within a single microcontroller circuit.
6. The circuit of claim 3 , wherein the power management reset circuit is further configured to generate the reset signal in response to monitoring of a microcontroller core power supply voltage.
This power management circuit for a microcontroller system features a flip-flop (processing an input and wake-up signal), a shutdown circuit (logically combining the flip-flop's output with a power supply sufficiency signal), and a power management reset circuit. This reset circuit generates a system reset signal for a microcontroller core and the flip-flop itself. To save power, the microcontroller core and the power management reset circuit are inactive during stand-by, and the wake-up signal activates them. In addition to being triggered by the shutdown circuit's output, the power management reset circuit can also generate this crucial reset signal if it detects issues by monitoring the power supply voltage specifically provided to the microcontroller core, enhancing system stability.
7. The circuit of claim 1 , wherein the power management reset circuit is not active in a stand-by mode of operation in order to save power and wherein the flip-flop and shutdown circuit remain active during the stand-by mode of operation.
This circuit, designed for intelligent power management, includes a flip-flop (receiving an input and a wake-up signal), a shutdown circuit (logically combining the flip-flop's output with a power supply sufficiency signal), and a power management reset circuit. The shutdown circuit's output triggers the power management reset circuit, which generates a system reset signal that also resets the flip-flop. A key feature for power saving is its stand-by mode: the power management reset circuit is inactive during stand-by to reduce consumption. However, the flip-flop and the shutdown circuit remain continuously active in stand-by, allowing them to detect the wake-up signal and initiate the process for the power management reset circuit to become active and perform its function.
8. The circuit of claim 1 , wherein the logic circuit of the shutdown circuit comprises: a logic gate having a first input configured to receive the first control signal and having a second input configured to receive the signal generated at the data output of the flip-flop.
This power management circuit consists of a flip-flop (receiving an input signal and a wake-up signal, with a data output), a shutdown circuit, and a power management reset circuit. The shutdown circuit contains a logic circuit that combines the flip-flop's data output with a first control signal (indicating a sufficient power supply voltage). This combined signal then triggers the power management reset circuit to generate a reset signal, which also resets the flip-flop. Specifically, the logic circuit within the shutdown circuit is implemented as a logic gate that has one input for the power supply sufficiency signal and another input for the signal coming directly from the flip-flop's data output, enabling precise control over system reset.
9. The circuit of claim 8 , wherein the logic gate is an AND gate.
This power management circuit includes a flip-flop (processing an input and wake-up signal, with a data output), a shutdown circuit, and a power management reset circuit. The shutdown circuit logically combines the flip-flop's data output with a first control signal (indicating a sufficient power supply voltage). This combined signal triggers the power management reset circuit to generate a reset signal for the system and the flip-flop. More specifically, the logic circuit within the shutdown circuit is a logic gate that receives the power supply sufficiency signal and the flip-flop's data output. This logic gate is an AND gate, ensuring that the next stage (the power management reset circuit) is only activated when both the flip-flop is in the correct state and the power supply is stable.
10. The circuit of claim 8 , wherein the logic circuit of the shutdown circuit further comprises: a supply monitoring circuit configured to monitor a power supply voltage and generate a second control signal when the monitored power supply voltage exceeds a threshold voltage; and a timing circuit configured to generate the first control signal from a time delay of the second control signal.
This power management circuit includes a flip-flop (receiving an input and wake-up signal, with a data output), a shutdown circuit, and a power management reset circuit. The shutdown circuit's logic combines the flip-flop's data output with a first control signal (indicating a sufficient power supply voltage). This combined signal then triggers the power management reset circuit to generate a reset signal for the system and the flip-flop. The logic circuit within the shutdown circuit is a logic gate that receives these two signals. Furthermore, this shutdown circuit elaborates on how the "first control signal" is generated: it contains a supply monitoring circuit that constantly checks the power supply voltage, generating an intermediate signal when the voltage exceeds a safe threshold. A timing circuit then receives this intermediate signal and delays it, producing the actual "first control signal" for the logic gate, ensuring a stable power state before enabling further operations.
11. The circuit of claim 10 , wherein the supply monitoring circuit operates to determine whether the power management reset circuit is active.
This power management circuit features a flip-flop, a shutdown circuit, and a power management reset circuit. The flip-flop processes an input and a wake-up signal. Its output, along with a first control signal (indicating sufficient power), is fed into a logic gate within the shutdown circuit. The output of this logic gate then triggers the power management reset circuit, which generates a system reset signal for the system and the flip-flop. The "first control signal" is generated by a supply monitoring circuit (which checks power supply voltage and signals when it's above a threshold) and then delayed by a timing circuit. Additionally, this supply monitoring circuit plays a further role: it is configured to determine if the power management reset circuit itself is currently active, likely by observing its power conditions.
12. The circuit of claim 11 , wherein the power management reset circuit is active when the power management reset circuit is not in a stand-by mode operation.
This power management circuit comprises a flip-flop (receiving an input and a wake-up signal, with a data output), a shutdown circuit, and a power management reset circuit. The shutdown circuit includes a logic gate that combines the flip-flop's output with a first control signal (indicating sufficient power supply voltage), triggering the power management reset circuit to generate a reset signal for the system and the flip-flop. This "first control signal" is derived from a supply monitoring circuit (which monitors voltage and generates an intermediate signal when above a threshold) delayed by a timing circuit. The supply monitoring circuit also checks if the power management reset circuit is active, which is explicitly defined as the state where the power management reset circuit is not in a stand-by mode of operation.
13. The circuit of claim 11 , wherein the supply monitoring circuit determines whether the power management reset circuit is active based on power supply voltage provided to the power management reset circuit.
This power management circuit includes a flip-flop, a shutdown circuit, and a power management reset circuit. The flip-flop processes an input and a wake-up signal, and its output is combined in a logic gate within the shutdown circuit with a first control signal (indicating sufficient power supply voltage). The output of this logic gate then triggers the power management reset circuit to generate a reset signal for the system and the flip-flop. The "first control signal" is generated by a supply monitoring circuit (which monitors voltage and signals when above a threshold) and then delayed by a timing circuit. The supply monitoring circuit determines if the power management reset circuit is active by specifically monitoring the power supply voltage that is delivered directly to the power management reset circuit itself.
14. The circuit of claim 1 , wherein the input signal is the voltage from the power supply.
This circuit is designed for robust power management. It comprises a flip-flop, a shutdown circuit with a logic circuit, and a power management reset circuit. The flip-flop receives an input signal and a wake-up signal, generating a data output. The shutdown circuit's logic combines this flip-flop output with a first control signal (indicating sufficient power supply voltage). This combined signal triggers the power management reset circuit, which then generates a reset signal for the system and also resets the flip-flop. Specifically, the input signal fed into the flip-flop is the direct voltage from the power supply, indicating that the flip-flop's initial state or operation can be directly influenced by the system's power status.
15. The circuit of claim 14 , wherein power supply to the power management reset circuit is stopped to save power in a stand-by mode of operation and wherein power supply to the flip-flop and shutdown circuit is not stopped during the stand-by mode of operation.
This power management circuit includes a flip-flop (whose input signal is the power supply voltage, and which also receives a wake-up signal), a shutdown circuit (logically combining the flip-flop's output with a power supply sufficiency signal), and a power management reset circuit. The shutdown circuit's output triggers the power management reset circuit to generate a system reset signal for the system and the flip-flop. To optimize power consumption, especially in stand-by mode, the power supply to the power management reset circuit is completely stopped. Conversely, the power supply to the flip-flop and the shutdown circuit is continuously maintained during stand-by, allowing them to remain active and ready to detect the wake-up signal to initiate the system's return to full operation.
16. The circuit of claim 1 , wherein the power management reset circuit is further configured to generate the reset signal in response to monitoring of the voltage of the power supply.
This circuit is designed for managing system resets and power states. It includes a flip-flop (which receives an input signal and a wake-up signal, with a data output), a shutdown circuit (containing a logic circuit that combines the flip-flop's output with a first control signal indicating a sufficient power supply voltage), and a power management reset circuit. The output of the shutdown circuit's logic triggers the power management reset circuit to generate a crucial system reset signal, which also resets the flip-flop. Furthermore, the power management reset circuit is equipped to generate this reset signal not only in response to the shutdown circuit's output but also if it detects any issues by directly monitoring the overall system power supply voltage, ensuring robust system stability.
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July 21, 2020
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