Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: processing circuitry to process instructions from a plurality of threads; a branch predictor storage structure shared between the plurality of threads and comprising a plurality of entries to store branch predictor information for predicting whether a branch instruction is to be taken or not taken or predicting a branch target address indicative of a next instruction to be fetched after the branch instruction when the branch instruction is to be taken, wherein the processing circuitry is configured to perform speculative processing assuming the predicted outcomes or branch target addresses of branch instructions are correct; and input mapping circuitry to map a received input value associated with a request from the processing circuitry to a modified input value for supply to the branch predictor storage structure; wherein the input mapping circuitry is configured to generate the modified input value as a function of the received input value and a key value selected depending on which of the plurality of threads triggered the request.
An apparatus features processing circuitry that handles instructions from multiple threads and performs speculative processing based on predicted branch outcomes. It includes a branch predictor storage structure, shared among these threads, which stores information for predicting whether a branch instruction will be taken, not taken, or its target address. To manage access to this shared storage, input mapping circuitry takes a received input value from the processing circuitry's request and generates a modified input value for the storage. This modified input value is calculated using a function that combines the received input value with a unique key value, where the specific key value chosen depends on which thread triggered the access request.
2. The apparatus according to claim 1 , in which the received input value comprises a requested index value corresponding to information to be accessed from the branch predictor storage structure, and the modified input value comprises a target index value identifying an entry of the storage structure to be accessed in response to the request from the processing circuitry.
This apparatus, as described above, contains processing circuitry handling multi-thread instructions and a shared branch predictor storage used for speculative processing based on branch predictions. Input mapping circuitry generates a modified input value for this storage based on a received input. Specifically, the received input value is a requested index value identifying desired information, and the modified input value is a target index value that precisely identifies which entry in the branch predictor storage structure should be accessed in response to the processing circuitry's request. This target index is generated as a function of the requested index value and a key value specific to the requesting thread.
3. The apparatus according to claim 1 , wherein the input mapping circuitry is configured to update the key value selected for at least one of the threads in response to a key updating event.
The apparatus previously described includes processing circuitry for multi-thread instructions and a shared branch predictor storage for speculative processing. Input mapping circuitry maps a received input value to a modified input value for this storage, generating it as a function of the received input value and a key value selected based on the requesting thread. Additionally, this input mapping circuitry is configured to update the specific key value assigned to at least one of the threads whenever a predefined "key updating event" occurs, allowing for dynamic adjustment of how threads access the shared branch predictor.
4. The apparatus according to claim 3 , wherein the key updating event comprises at least one of: elapse of a predetermined period since a previous key updating event; a context switch; and at least one performance metric satisfying at least one predetermined condition, said at least one performance metric indicative of a level of contention between threads for entries of the branch predictor storage structure.
This apparatus features processing circuitry for multi-thread instructions, a shared branch predictor storage for speculative processing, and input mapping circuitry. The input mapping circuitry maps a received input value to a modified input value using a function of the received input and a thread-specific key value, and updates this key value for at least one thread when a "key updating event" occurs. Such a key updating event can include the lapse of a predetermined time since the last key update, a context switch between threads, or when a performance metric (like the level of contention between threads for branch predictor entries) satisfies a predetermined condition, indicating a need to re-randomize access.
5. The apparatus according to claim 1 , wherein the key value is dependent on a random or pseudorandom number.
The apparatus includes processing circuitry for multi-thread instructions, a shared branch predictor storage for speculative processing, and input mapping circuitry. This input mapping circuitry maps a received input value to a modified input value for the storage. The modified input value is generated as a function of the received input value and a key value chosen based on the requesting thread. Crucially, this thread-specific key value is determined by, or derived from, a random or pseudorandom number, providing a dynamic and unpredictable element to how threads access the shared branch predictor.
6. The apparatus according to claim 1 , comprising a plurality of pseudorandom number generators each corresponding to one of the plurality of threads; wherein the input mapping circuitry is configured to select, as the key value to be used for generating the modified input value, a pseudorandom number generated by the pseudorandom number generator corresponding to the thread that triggered the request.
This apparatus comprises processing circuitry for multi-thread instructions and a shared branch predictor storage for speculative processing. Input mapping circuitry maps a received input value to a modified input value for the storage, generating it as a function of the received input value and a thread-specific key value. To implement this, the apparatus also includes multiple pseudorandom number generators, with each generator corresponding to one of the threads. The input mapping circuitry selects the key value for generating the modified input value by taking the pseudorandom number produced by the generator that corresponds to the thread making the current request.
7. The apparatus according to claim 6 , wherein in response to a key updating event, the input mapping circuitry is configured to control each of the plurality of pseudorandom number generators to update its pseudorandom number.
The apparatus features processing circuitry for multi-thread instructions, a shared branch predictor storage for speculative processing, and input mapping circuitry. This mapping circuitry generates a modified input value for the storage from a received input value and a thread-specific key, selected from a dedicated pseudorandom number generator for that thread. Furthermore, in response to a key updating event, the input mapping circuitry is configured to control *each* of these dedicated pseudorandom number generators to update their respective pseudorandom numbers, ensuring that all threads' keys can be refreshed simultaneously or in coordinated fashion.
8. The apparatus according to claim 2 , wherein the requested index value is dependent on a virtual address.
This apparatus includes processing circuitry for multi-thread instructions and a shared branch predictor storage used for speculative processing based on branch predictions. Input mapping circuitry maps a received input value, which is a requested index value, to a modified input value, which is a target index value for an entry in the storage. This target index is generated as a function of the requested index value and a key value specific to the requesting thread. Importantly, the initial requested index value that the processing circuitry provides is itself dependent on a virtual address, linking the branch predictor access mechanism to the program's virtual memory space.
9. The apparatus according to claim 1 , wherein in a first mode, the input mapping circuitry is configured to generate the modified input value as a function of the received input value and the key value selected depending on which of the plurality of threads triggered the request; and in a second mode, the input mapping circuitry is configured to generate the modified input value from the received input value independent of which of the plurality of threads triggered the request.
The apparatus contains processing circuitry for multi-thread instructions and a shared branch predictor storage for speculative processing. Input mapping circuitry maps a received input value to a modified input value for this storage. This circuitry can operate in two modes: In a "first mode," it generates the modified input value as a function of the received input value and a key value chosen based on which thread triggered the request (as described in the core invention). In a "second mode," however, the input mapping circuitry generates the modified input value solely from the received input value, completely independent of which thread made the request, bypassing the thread-specific key.
10. The apparatus according to claim 9 , wherein the input mapping circuitry is configured to select whether to use the first mode or the second mode in dependence on the received input value.
This apparatus, with its processing circuitry handling multi-thread instructions and shared branch predictor storage, includes input mapping circuitry that can operate in two modes: a "first mode" using a thread-specific key to generate a modified input value, and a "second mode" generating the modified input value without considering the requesting thread. Furthermore, the input mapping circuitry is configured to actively choose whether to operate in the first mode or the second mode. This selection is made dynamically based on the specific received input value supplied by the processing circuitry, allowing adaptive behavior for branch predictor access.
11. The apparatus according to claim 9 , wherein in the first mode, the input mapping circuitry is configured to generate a first portion of the modified input value as a function of a first portion of the received input value and the key value, and to generate a second portion of the modified input value using a direct mapping from a second portion of the received input value.
The apparatus features processing circuitry for multi-thread instructions and a shared branch predictor storage for speculative processing. Input mapping circuitry maps a received input value to a modified input value for the storage, operating in two modes: a "first mode" using a thread-specific key and a "second mode" without it. In the "first mode," the generation of the modified input value is segmented: a first portion of the modified input value is generated by applying the function to a first portion of the received input value and the thread-specific key. Concurrently, a second portion of the modified input value is generated using a direct, unmodified mapping from a second portion of the received input value.
12. The apparatus according to claim 1 , wherein the processing circuitry comprises a processing pipeline to process instructions from the plurality of threads with instructions from multiple threads in flight in the processing pipeline concurrently.
An apparatus includes processing circuitry that processes instructions from multiple threads, capable of speculative processing based on predicted branch outcomes. It also has a branch predictor storage structure, shared among these threads, which stores information for predicting branch behavior. Input mapping circuitry generates a modified input value for this storage as a function of a received input value and a thread-specific key value. A key characteristic of this apparatus is that the processing circuitry itself comprises a processing pipeline designed to handle instructions from the plurality of threads such that instructions from multiple different threads can be actively "in flight" and processed concurrently within the pipeline.
13. The apparatus according to claim 1 , wherein said function comprises a hash function which provides a one-to-one mapping between the received input value and the modified input value.
This apparatus contains processing circuitry for multi-thread instructions and a shared branch predictor storage for speculative processing. Input mapping circuitry generates a modified input value for the storage from a received input value and a thread-specific key value. The specific mathematical "function" used by the input mapping circuitry to combine the received input value and the key value is a hash function. This hash function is designed to provide a one-to-one mapping, meaning that each unique combination of received input and key value will deterministically produce a unique modified input value, ensuring efficient and distinct access patterns.
14. The apparatus according to claim 13 , wherein said function comprises XOR.
The apparatus features processing circuitry for multi-thread instructions, a shared branch predictor storage for speculative processing, and input mapping circuitry that generates a modified input value from a received input and a thread-specific key using a hash function that provides a one-to-one mapping. Specifically, the mathematical "function" that implements this one-to-one hash mapping is an XOR operation. This means the input mapping circuitry uses a bitwise XOR operation to combine the received input value and the key value, producing the modified input value for accessing the branch predictor storage.
15. An apparatus comprising: means for processing instructions from a plurality of threads; means for branch predictor storage shared between the plurality of threads and comprising a plurality of entries for storing branch predictor information for predicting whether a branch instruction is to be taken or not taken or predicting a branch target address indicative of a next instruction to be fetched after the branch instruction when the branch instruction is to be taken, wherein the means for processing instructions is configured to perform speculative processing assuming the predicted outcomes or branch target addresses of branch instructions are correct; and means for mapping a received input value associated with a request from the means for processing to a modified input value for supply to the means for branch predictor storage; wherein the means for mapping is configured to generate the modified input value as a function of the received input value and a key value selected depending on which of the plurality of threads triggered the request.
An apparatus comprises processing circuitry for handling instructions from multiple threads and performing speculative processing based on branch predictions. It includes a shared branch predictor storage for storing branch prediction information. Furthermore, it has input mapping circuitry configured to map a received input value, associated with a request from the processing circuitry, to a modified input value for accessing the branch predictor storage. The input mapping circuitry generates this modified input value as a mathematical function of the received input value and a key value, where the specific key value selected depends on which of the threads triggered the access request, aiming to distribute accesses within the shared storage.
16. A data processing method comprising: processing instructions from a plurality of threads on processing circuitry; storing, in a plurality of entries of a branch predictor storage structure shared between the plurality of threads, branch predictor information for predicting whether a branch instruction is to be taken or not taken or predicting a branch target address indicative of a next instruction to be fetched after the branch instruction when the branch instruction is to be taken, wherein speculative processing is performed by the processing circuitry assuming the predicted outcomes or branch target addresses of branch instructions are correct; and mapping a received input value associated with a request from the processing circuitry to a modified input value for supply to the branch predictor storage structure; wherein the modified input value is generated as a function of the received input value and a key value selected depending on which of the plurality of threads triggered the request.
A data processing method involves processing instructions from multiple threads on processing circuitry, which also performs speculative processing based on predicted branch outcomes. Branch predictor information is stored in a shared branch predictor storage structure, which has multiple entries and is accessible by all threads. The method includes mapping a received input value, which is part of an access request from the processing circuitry, to a modified input value intended for the branch predictor storage. This modified input value is generated by applying a function that combines the received input value with a key value, where the key value is specifically chosen based on which of the plurality of threads triggered the original access request.
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July 28, 2020
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