10729309

Endoscope System

PublishedAugust 4, 2020
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
3 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. An endoscope system, comprising: a first processor configured to perform first image processing on a set of image data, and output the set of image data that has been subjected to the first image processing, the set of image data being one of: two sets of image data having object image acquisition areas that are at least partially different from each other; or two sets of image data having a parallax from each other for a common object; a second processor configured to perform second image processing on another set of image data, and output the other set of image data that has been subjected to the second image processing, the other set of image data being other one of: the two sets of image data having the object image acquisition areas that are at least partially different from each other; or the two sets of image data having the parallax from each other for the common object; a third processor that is provided in a housing separately bodied from a housing or housings where the first processor and the second processor are provided, the third processor being configured to generate, based on the set of image data output from the first processor and on the other set of image data output from the second processor, display image data to be displayed on a display; a recorder configured to record therein image data based on the set of image data output from the first processor and on the other set of image data output from the second processor; a fourth processor that is provided in the housing where the first processor or the second processor is provided, the fourth processor being configured to generate a first synchronization signal for synchronization among the first processor, the second processor, and the third processor; a fifth processor that is provided in the housing where the third processor is provided, the fifth processor being configured to generate a second synchronization signal for synchronization between at least the third processor and the recorder; and a controller configured to select one of the first synchronization signal generated by the fourth processor and the second synchronization signal generated by the fifth processor, and perform control for synchronization between the third processor and the recorder.

Plain English Translation

An endoscope system processes and displays images, potentially from different views or for stereo vision. It uses a first processor for initial image processing on one image data set and a second processor for another, where these two sets either cover partially different acquisition areas or provide parallax for a common object. A third processor, located in a separate housing, combines these processed outputs to generate display images. A recorder also stores image data based on these processed outputs. Synchronization is managed by two distinct signals: a fourth processor (in the same housing as the first or second processor) generates a first signal for global synchronization among the first, second, and third processors. A fifth processor (in the same housing as the third processor) generates a second signal for synchronizing at least the third processor and the recorder. A controller selects between these two synchronization signals to specifically manage timing between the third processor and the recorder.

Claim 2

Original Legal Text

2. The endoscope system according to claim 1 , wherein when the housing where the fourth processor is provided and the housing where the third processor is provided are electrically connected to each other, the controller is configured to select the first synchronization signal generated by the fourth processor.

Plain English Translation

This endoscope system processes and displays images, potentially from different views or for stereo vision. It uses a first processor for initial image processing on one image data set and a second processor for another, where these two sets either cover partially different acquisition areas or provide parallax for a common object. A third processor, located in a separate housing, combines these processed outputs to generate display images. A recorder also stores image data based on these processed outputs. Synchronization is managed by two distinct signals: a fourth processor (in the same housing as the first or second processor) generates a first signal for global synchronization among the first, second, and third processors. A fifth processor (in the same housing as the third processor) generates a second signal for synchronizing at least the third processor and the recorder. A controller selects between these two signals to manage timing between the third processor and the recorder. Specifically, when the housing containing the fourth processor and the housing containing the third processor are electrically connected, the controller selects the first synchronization signal from the fourth processor to synchronize the third processor and the recorder.

Claim 3

Original Legal Text

3. The endoscope system according to claim 1 , wherein when the housing where the fourth processor is provided and the housing where the third processor is provided are not electrically connected to each other, the controller is configured to select the second synchronization signal generated by the fifth processor.

Plain English Translation

This endoscope system processes and displays images, potentially from different views or for stereo vision. It uses a first processor for initial image processing on one image data set and a second processor for another, where these two sets either cover partially different acquisition areas or provide parallax for a common object. A third processor, located in a separate housing, combines these processed outputs to generate display images. A recorder also stores image data based on these processed outputs. Synchronization is managed by two distinct signals: a fourth processor (in the same housing as the first or second processor) generates a first signal for global synchronization among the first, second, and third processors. A fifth processor (in the same housing as the third processor) generates a second signal for synchronizing at least the third processor and the recorder. A controller selects between these two signals to manage timing between the third processor and the recorder. Specifically, when the housing containing the fourth processor and the housing containing the third processor are not electrically connected, the controller selects the second synchronization signal from the fifth processor to synchronize the third processor and the recorder.

Patent Metadata

Filing Date

Unknown

Publication Date

August 4, 2020

Inventors

Koji KOJIMA
Hideyuki KUGIMIYA
Ryo KOSHIDA

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