Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data drive device in a display device, the data drive device comprising: a data reception circuit configured to train a communication clock according to a received clock pattern, to receive first link data in accordance with the communication clock, to train a data link according to the first link data, to receive image data in a plurality of image reception periods within one frame period, to sort the image data in accordance with the data link, to receive second link data in a link reception period disposed between the plurality of image reception periods, and to retrain the data link according to the second link data; and a data voltage drive circuit configured to generate a data voltage by converting the image data and to supply the data voltage to each sub-pixel.
Display device technology. This invention addresses the challenge of efficiently and reliably transferring image data to display sub-pixels. The system includes a data drive device integrated within a display device. This device comprises a data reception circuit and a data voltage drive circuit. The data reception circuit is designed to establish a communication link. It first trains a communication clock by analyzing a received clock pattern. Using this trained clock, it receives initial link data. This first set of link data is then used to train a data link. Subsequently, image data is received over multiple image reception periods within a single frame period. The data reception circuit sorts this image data according to the established data link. Crucially, it also receives second link data during a specific link reception period that occurs between the image data reception periods. This second link data is then used to retrain the data link, ensuring ongoing accuracy and stability. The data voltage drive circuit takes the processed image data, converts it into a data voltage, and then supplies this voltage to each sub-pixel of the display. This enables the display to render the image accurately.
2. The data drive device of claim 1 , wherein the one frame period comprises a plurality of horizontal (H) time periods respectively corresponding to a plurality of lines on a display panel, and the plurality of H time periods comprise a setting reception period for receiving setting data, the image reception period, and the link reception period.
A data drive device is designed to control data transmission to a display panel, addressing challenges in efficiently managing data transfer and synchronization in display systems. The device includes a data driver configured to receive and process data for display, with a frame period divided into multiple horizontal (H) time periods corresponding to individual lines on the display panel. Each frame period includes distinct time segments: a setting reception period for receiving configuration data, an image reception period for receiving image data, and a link reception period for receiving synchronization or control data. This structured division ensures efficient data handling, reducing latency and improving synchronization between the data driver and the display panel. The device optimizes data flow by allocating specific time slots for different types of data, enhancing overall display performance and reliability. The invention is particularly useful in high-resolution or high-refresh-rate displays where precise timing and data management are critical.
3. The data drive device of claim 2 , wherein, when the data link that is determined as an error is restored in the link reception period of a Jth H time period (J is a natural number) among the plurality of H time periods, a process corresponding to the setting reception period or the image reception period of a (J+1)th H time period is normally performed subsequently.
This invention relates to data drive devices used in display systems, particularly those handling data transmission errors during link restoration. The problem addressed is ensuring seamless data processing when a data link temporarily fails and is later restored, preventing disruptions in display operations. The device includes a data link that transmits data in multiple time periods (H time periods). If an error occurs in a data link during a specific time period, the device detects the error and skips processing for that period. When the link is restored in a subsequent Jth H time period (where J is a positive integer), the device resumes normal operations in the next (J+1)th H time period. This ensures that data processing for subsequent periods (such as setting or image reception) proceeds without interruption, maintaining display continuity. The invention improves reliability in data transmission by dynamically adjusting to link errors and restoring normal operations once the link is back online, preventing data loss or display artifacts. This is particularly useful in high-speed data transmission systems where link stability is critical.
4. The data drive device of claim 1 , wherein the data reception circuit checks the image data or the second link data, and generates a fail signal when the image data or the second link data is against a predefined rule.
This invention relates to a data drive device for transmitting image data and link data between devices, addressing the problem of ensuring data integrity and compliance with predefined rules during transmission. The device includes a data reception circuit that receives image data and second link data from a transmission circuit. The data reception circuit checks the received data against predefined rules, such as format, size, or content restrictions. If the data violates these rules, the circuit generates a fail signal to indicate the error. This ensures that only valid data is processed, preventing errors in subsequent operations. The device may also include a transmission circuit that converts image data into a specific format for transmission, ensuring compatibility between devices. The transmission circuit may also generate first link data, which is transmitted alongside the image data to establish a connection or provide metadata. The data reception circuit processes both the image data and the second link data, verifying their integrity before further use. The fail signal can trigger corrective actions, such as retransmission or error logging, to maintain system reliability. This invention improves data transmission accuracy and system robustness by enforcing predefined rules at the reception stage.
5. The data drive device of claim 4 , wherein the data reception circuit counts the fail signal, and changes a state of a lock signal connected to an outside when the fail signal occurs N times or more (N is a natural number).
A data drive device includes a data reception circuit that processes received data and generates a fail signal when an error is detected. The data reception circuit counts occurrences of the fail signal and changes the state of a lock signal connected to an external system when the fail signal occurs N times or more, where N is a natural number. This lock signal can be used to indicate a persistent error condition, allowing the external system to take corrective action, such as disabling further data transmission or triggering a reset. The device may also include a data transmission circuit that sends data to an external system, and a control circuit that manages operations based on the lock signal state. The fail signal may be generated when data reception fails to meet predefined criteria, such as signal integrity or timing requirements. The lock signal change provides a mechanism to prevent further data corruption or system malfunctions by alerting the external system of repeated errors. This approach enhances reliability in data transmission systems by ensuring that persistent errors are detected and addressed.
6. The data drive device of claim 5 , wherein the data reception circuit retrains the communication clock and the data link when changing the state of the lock signal.
This invention relates to data drive devices, specifically those used in high-speed data communication systems where maintaining synchronization between a host device and a storage device is critical. The problem addressed is ensuring reliable data transfer when the communication link needs to be reset or reconfigured, such as during power management transitions or error recovery. Existing systems may experience data corruption or communication failures when adjusting the lock signal that controls the data link state. The invention describes a data drive device with a data reception circuit that actively retrains the communication clock and data link whenever the lock signal changes state. The lock signal is used to control the activation or deactivation of the data link, such as during power-saving modes or error recovery procedures. When the lock signal transitions (e.g., from active to inactive or vice versa), the data reception circuit automatically retrains the clock and data link to reestablish synchronization. This ensures that the communication link remains stable and data integrity is maintained during state changes. The retraining process may involve resynchronizing the clock phase and frequency, reconfiguring data link parameters, or reinitializing the communication protocol. This feature is particularly useful in systems where the data link must frequently switch between active and low-power states, such as in mobile or energy-efficient storage devices. The invention improves reliability and reduces errors in data transmission by dynamically adapting to changes in the lock signal state.
7. The data drive device of claim 1 , wherein the data reception circuit trains the communication clock by a phase-locked loop (PLL) method.
This invention relates to data drive devices, specifically focusing on improving data reception in communication systems. The problem addressed is the need for precise synchronization between a data drive device and a transmitting device to ensure accurate data reception. Traditional methods often suffer from clock mismatches, leading to data errors or transmission failures. The invention describes a data drive device with a data reception circuit that includes a phase-locked loop (PLL) for training the communication clock. The PLL dynamically adjusts the clock signal to align with the incoming data stream, compensating for phase and frequency variations. This ensures reliable data reception even under varying transmission conditions. The data reception circuit may also include a data extraction circuit that processes the received data stream to recover the transmitted information. The PLL method enhances synchronization by continuously monitoring and correcting the clock signal, reducing errors caused by timing discrepancies. This approach is particularly useful in high-speed or noisy communication environments where maintaining clock alignment is challenging. By integrating a PLL into the data reception circuit, the invention provides a robust solution for maintaining synchronization in data drive devices, improving overall communication reliability and performance.
8. The data drive device of claim 1 , wherein the data reception circuit sorts the image data per byte, decodes the image data sorted per byte into a DC balance code, descrambles the decoded image data, and sorts the descrambled image data per pixel.
This invention relates to a data drive device for processing image data in a display system. The device addresses the challenge of efficiently handling and transmitting image data to ensure accurate and reliable display. The data drive device includes a data reception circuit that receives image data and processes it through multiple stages to prepare it for display. The circuit first sorts the incoming image data by byte, which organizes the data into a structured format for further processing. The sorted data is then decoded into a DC balance code, a technique used to maintain signal integrity by balancing the number of positive and negative voltage levels in the data stream. After decoding, the data undergoes descrambling to reverse any intentional scrambling applied during transmission, restoring the original data sequence. Finally, the descrambled data is sorted per pixel, aligning the data with the pixel structure of the display for accurate rendering. This multi-stage processing ensures that the image data is correctly formatted, balanced, and organized for optimal display performance. The invention enhances data transmission efficiency and display accuracy in electronic display systems.
9. The data drive device of claim 1 , wherein the first link data and the second link data comprise a plurality of symbols, and the data reception circuit sorts the image data per byte using one symbol among the plurality of symbols and sorts the image data per pixel using at least two or more symbols among the plurality of symbols.
A data drive device is used in display systems to process and transmit image data efficiently. The device addresses the challenge of organizing image data for accurate and rapid display, particularly in systems where data must be sorted both by byte and by pixel. The device includes a data reception circuit that receives image data along with link data, which contains symbols used for sorting. The link data comprises multiple symbols, where one symbol is used to sort the image data by byte, and at least two or more symbols are used to sort the image data by pixel. This dual sorting mechanism ensures that the image data is correctly aligned and processed for display, improving data transmission efficiency and reducing errors. The device may also include a data transmission circuit that transmits the sorted image data to a display panel, ensuring that the data is displayed accurately. The sorting process is essential for maintaining synchronization between the data drive device and the display panel, particularly in high-resolution or high-speed display applications. The use of multiple symbols for pixel-level sorting allows for precise control over data placement, enhancing display quality and performance.
10. The data drive device of claim 1 , wherein the data voltage drive circuit supplies the data voltage in the link reception period.
This invention relates to data drive devices used in display systems, specifically addressing the challenge of efficiently managing data voltage during link reception periods. The device includes a data voltage drive circuit that provides a data voltage to a display panel. The key improvement is that the data voltage drive circuit supplies this voltage specifically during the link reception period, which is the time when data is being received from an external source. This ensures that the display panel receives the correct voltage at the right time, improving synchronization and reducing power consumption by avoiding unnecessary voltage supply outside the reception period. The device also includes a data voltage generation circuit that generates the required voltage levels, and a data voltage selection circuit that selects the appropriate voltage based on the received data. The data voltage drive circuit then drives the selected voltage to the display panel during the link reception period. This approach optimizes the timing of voltage application, enhancing display performance and efficiency. The invention is particularly useful in high-speed data transmission systems where precise timing and power management are critical.
11. The data drive device of claim 1 , wherein the data voltage drive circuit supplies the data voltage according to a periodic signal indicating one point in the link reception period.
A data drive device is used in communication systems to transmit data signals over a communication link. The device includes a data voltage drive circuit that generates and supplies a data voltage to a transmission line. The data voltage is modulated to represent digital data for transmission. A key challenge in such systems is ensuring accurate timing and synchronization of the data voltage with the receiver's sampling points to minimize errors. The data drive device includes a periodic signal generator that produces a periodic signal synchronized with the link reception period. This signal indicates a specific point within the reception period, which is used to control the timing of the data voltage supplied by the drive circuit. The periodic signal ensures that the data voltage is applied at the correct moment, aligning with the receiver's sampling window. This synchronization improves data integrity and reduces transmission errors caused by misalignment. The data voltage drive circuit may include components such as voltage regulators, amplifiers, and timing control logic to generate and adjust the data voltage based on the periodic signal. The periodic signal can be derived from a clock signal or other timing reference, ensuring precise synchronization with the receiver's operations. This approach enhances the reliability of data transmission in high-speed communication links.
12. The data drive device of claim 1 , wherein the data voltage has a greater voltage range than that of the image data or the link data.
This invention relates to a data drive device used in display systems, particularly for driving display panels with both image data and additional data such as link data. The problem addressed is the need to transmit high-voltage data signals alongside standard image data without requiring separate drive circuits or increasing power consumption. The data drive device includes a data voltage generator that produces a data voltage with a wider voltage range than the standard image data or link data. This allows the device to handle high-voltage signals, such as those used in touch sensing or other auxiliary functions, while maintaining compatibility with conventional display driving. The device also includes a data output circuit that selectively outputs either the image data or the link data based on control signals, ensuring efficient data transmission without signal interference. The voltage range adjustment ensures that high-voltage signals do not degrade image quality or require additional power. By integrating high-voltage data transmission into a single drive device, this invention simplifies display system design, reduces component count, and improves energy efficiency. The solution is particularly useful in touchscreen displays where both image and touch data must be processed simultaneously. The invention ensures reliable data transmission while maintaining display performance.
13. The data drive device of claim 1 , wherein the data reception circuit checks the image data or the second link data, generates a fail signal when the image data or the second link data is against a predefined rule, changes a state of a lock signal connected to an outside when the fail signal occurs N times or more (N is a natural number), and re-receives the clock pattern after changing the state of the lock signal.
This invention relates to a data drive device for handling image data and link data in a display system. The device addresses the problem of ensuring data integrity and synchronization in high-speed data transmission, particularly when errors occur in the received data. The data drive device includes a data reception circuit that checks incoming image data or second link data against predefined rules. If the data violates these rules, the circuit generates a fail signal. When the fail signal occurs N times (where N is a natural number), the circuit changes the state of a lock signal connected to an external system, indicating a synchronization or data error. After changing the lock signal state, the device re-receives a clock pattern to attempt re-synchronization. This mechanism helps maintain reliable data transmission by detecting and recovering from errors, ensuring that the display system operates correctly even under adverse conditions. The invention improves fault tolerance and data integrity in display systems by dynamically adjusting to transmission errors.
14. A data processing device comprising: a data processor configured to encode image data; and a data transmitter configured to transmit a clock pattern, to transmit first link data, to transmit the image data in a plurality of image transmission periods within one frame period, to transmit second link data in a link transmission period disposed between the plurality of image transmission periods, and to retransmit the clock pattern and the first link data when a state of a received lock signal is changed.
This invention relates to a data processing device for transmitting image data in a structured format. The device addresses the challenge of efficiently transmitting image data while maintaining synchronization and ensuring data integrity in communication systems. The device includes a data processor that encodes image data and a data transmitter that manages the transmission process. The transmitter sends a clock pattern to establish timing synchronization, followed by first link data containing control or configuration information. The image data is transmitted in multiple segments (image transmission periods) within a single frame period. Between these segments, second link data is transmitted in a dedicated link transmission period, allowing for additional control or status updates. If the state of a received lock signal changes, indicating a potential synchronization issue, the device retransmits the clock pattern and the first link data to restore synchronization and ensure reliable communication. This approach improves transmission robustness by dynamically adjusting to synchronization errors while maintaining efficient data flow.
15. The data processing device of claim 14 , wherein the one frame period comprises a plurality of horizontal (H) time periods respectively corresponding to a plurality of lines on a display panel, and the plurality of H time periods comprise a setting reception period for receiving setting data, the image reception period, and the link reception period.
This invention relates to data processing devices for display panels, specifically addressing the challenge of efficiently managing data transmission and synchronization in display systems. The device processes data for a display panel by dividing a frame period into multiple horizontal (H) time periods, each corresponding to a line on the display. These H time periods include distinct phases: a setting reception period for receiving configuration or control data, an image reception period for receiving image data, and a link reception period for receiving additional data or commands. The device ensures synchronized data handling by allocating specific time slots for each type of data, improving display performance and reducing errors. The invention optimizes data flow by separating different data types into dedicated periods, enhancing efficiency and reliability in display panel operation. This approach is particularly useful in systems requiring precise timing and coordination between data transmission and display updates.
16. A display drive system comprising: a data processing device configured to transmit a clock pattern, to transmit first link data, to transmit image data in a plurality of image transmission periods within one frame period, and to transmit second link data in a link transmission period disposed between the image transmission periods; and a data drive device configured to train a communication clock according to the received clock pattern, to receive the first link data in accordance with the communication clock, to train a data link according to the first link data, to receive the image data in a plurality of image reception periods, to sort the image data in accordance with the data link, to receive the second link data in a link reception period disposed between the plurality of image reception periods, and to retrain the data link according to the second link data.
This invention relates to a display drive system designed to improve data transmission efficiency and reliability in display technologies. The system addresses the challenge of maintaining synchronized and error-free data transfer between a data processing device and a data drive device, particularly in high-resolution or high-refresh-rate displays where data integrity and timing are critical. The system includes a data processing device that transmits a clock pattern to synchronize communication, followed by first link data to establish an initial data link. Image data is then transmitted in multiple segments (image transmission periods) within a single frame period, with second link data sent between these segments to periodically retrain the data link. This segmented approach ensures continuous data flow while allowing for real-time adjustments to maintain link stability. The data drive device receives the clock pattern to train its communication clock, then uses the first link data to establish the initial data link. It processes the segmented image data in corresponding image reception periods, sorting the data according to the established link. Between these periods, it receives the second link data to retrain the link, compensating for any drift or errors that may occur during transmission. This dynamic retraining mechanism enhances data integrity and reduces the risk of synchronization loss, particularly in demanding display applications. The system optimizes bandwidth usage by interleaving link maintenance with image data transmission, ensuring efficient and reliable display operation.
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September 8, 2020
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