Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory system, comprising: a memory including a plurality of areas; and a controller circuit configured to: during a write operation to write data to an area among the plurality of areas, encode first data to be written to at a first code rate, change a code rate with regard to the area from the first code rate to a second code rate that is less than the first code rate when a condition for changing the code rate with regard to the area is satisfied, and during a next write operation to write data to the area, encode second data to be written to the area at the second code rate, after changing the first code rate to the second code rate, wherein the condition for the changing the code rate includes: a number of erase operations processed for the area reaching a predetermined number, and a certain amount of time elapsing since programming the first data to the area.
The memory system addresses the problem of maintaining data integrity and reliability in non-volatile memory as it ages. Over time, memory cells degrade due to repeated erase and write cycles, leading to higher error rates. The system dynamically adjusts the error correction coding (ECC) rate to compensate for this degradation. The memory includes multiple areas, and a controller circuit manages the encoding process. During a write operation, data is initially encoded at a first code rate. If a condition is met—either the area has undergone a predetermined number of erase operations or a certain time has elapsed since the last write—the controller switches to a second, lower code rate (stronger ECC) for subsequent writes to that area. This adaptive approach ensures higher reliability for aged memory cells while optimizing storage efficiency for newer cells. The system balances performance and endurance by dynamically adjusting the ECC strength based on usage and time, extending the lifespan of the memory.
2. The memory system according to claim 1 , wherein the controller circuit is further configured to: during a read operation to read the first data from the area before changing the code rate with regard to the area from the first code rate to the second code rate, decode the first data read from the area at the first code rate, and change the code rate with regard to the area from the first code rate to the second code rate, upon the condition being satisfied and the number of error bits during the read operation of the first data being above a first threshold number.
A memory system includes a controller circuit that manages data storage and retrieval in a memory area. The system addresses the challenge of maintaining data integrity and efficiency when adjusting error correction coding rates. The controller is configured to perform read operations from a memory area initially encoded at a first code rate. During these operations, the controller decodes the data using the first code rate. If a condition is met—such as a high error rate—and the number of error bits detected during the read operation exceeds a first threshold, the controller changes the code rate for that area from the first rate to a second rate. This adjustment improves error correction performance for subsequent operations. The system ensures reliable data access by dynamically adapting the code rate based on error conditions, optimizing between storage efficiency and error resilience. The controller's ability to assess error rates during read operations allows for proactive adjustments, preventing data loss and maintaining system reliability. This approach is particularly useful in memory systems where varying error rates may occur due to factors like wear or environmental conditions.
3. The memory system according to claim 2 , wherein the controller circuit is further configured to: change the code rate with regard to the area from the first code rate to a third code rate that is less than the second code rate, upon the condition being satisfied and the number of error bits during the read operation of the first data being above a second threshold number that is greater than the first threshold number.
The invention relates to memory systems, specifically to improving error correction in non-volatile memory (NVM) devices. The problem addressed is the inefficiency of fixed error correction schemes in handling varying error rates across different memory areas, leading to either excessive overhead or insufficient error correction. The memory system includes a controller circuit that adjusts the error correction code (ECC) rate dynamically based on error conditions detected during read operations. The controller monitors error bits in read data and compares them against predefined thresholds. If the error rate exceeds a first threshold, the ECC rate is increased from a first rate to a second, higher rate to enhance error correction. If the error rate further exceeds a second, higher threshold, the ECC rate is reduced to a third rate, lower than the second but potentially higher than the first, to balance correction strength and overhead. The system also includes a memory device with multiple areas, where each area may experience different error rates due to factors like wear or manufacturing variations. The controller tracks error rates per area and adjusts the ECC rate accordingly, optimizing performance and reliability. This dynamic adjustment prevents unnecessary overhead in low-error areas while ensuring robust correction in high-error regions. The invention improves memory system efficiency by adapting error correction to real-time conditions.
4. The memory system according to claim 3 , wherein the controller circuit is further configured to: invalidate the area upon determining that the number of error bits during the read operation is above a third threshold number that is greater than the second threshold number.
A memory system includes a controller circuit that manages data storage and retrieval operations. The system addresses the challenge of maintaining data integrity in non-volatile memory, particularly when errors occur during read operations. The controller circuit is configured to detect and handle errors by comparing the number of error bits in read data against predefined thresholds. If the number of error bits exceeds a first threshold, the system performs error correction. If the error count surpasses a second, higher threshold, the system marks the affected memory area as unreliable. Additionally, if the error count exceeds a third, even higher threshold, the system invalidates the area entirely, preventing further use of that memory region. This progressive error-handling approach ensures data reliability by dynamically adjusting responses based on error severity, thereby extending the usable lifespan of the memory while minimizing data loss risks. The system is particularly useful in storage devices where maintaining data integrity is critical, such as solid-state drives or embedded memory systems.
5. The memory system according to claim 2 , wherein the controller circuit is further configured to: perform a threshold voltage tracking operation to determine the read voltage for the read operation.
A memory system includes a controller circuit configured to manage data storage and retrieval operations in a non-volatile memory array. The system addresses challenges in accurately reading stored data, particularly as memory cells degrade over time, leading to shifts in their threshold voltages. The controller circuit performs a threshold voltage tracking operation to dynamically adjust read voltages during read operations. This tracking operation involves monitoring changes in the threshold voltages of memory cells and updating the read voltage levels accordingly to ensure reliable data retrieval. The system may also include error correction mechanisms to further enhance data integrity. By continuously tracking and adjusting read voltages, the memory system maintains accurate data access even as memory cells age or experience wear. This approach improves read reliability and extends the lifespan of the memory device. The controller circuit may also manage other operations such as programming and erasing data, ensuring efficient and accurate memory management. The threshold voltage tracking operation helps mitigate the effects of cell degradation, ensuring consistent performance over the memory device's lifetime.
6. The memory system according to claim 1 , wherein the area comprises a plurality of memory cells, and the controller circuit is further configured to: process a read operation to read the first data from the area before changing the code rate with regard to the area from the first code rate to the second code rate, and change the code rate from the first code rate to the second code rate, upon the condition being satisfied and the number of memory cells having a threshold voltage within a voltage range that includes an optimum read voltage within overlapped threshold voltage distributions being above a first threshold number.
This invention relates to memory systems, specifically addressing the challenge of optimizing data reliability and storage efficiency in non-volatile memory devices. The system includes a memory area with multiple memory cells and a controller circuit that dynamically adjusts the code rate used for error correction based on the condition of the memory cells. The controller first reads data from the area before changing the code rate from a first rate to a second rate. The change occurs only if a specific condition is met and if the number of memory cells with threshold voltages within a voltage range—including an optimum read voltage—exceeds a predefined threshold. This voltage range is defined by overlapping threshold voltage distributions, which can indicate increased error susceptibility. By dynamically adjusting the code rate based on these conditions, the system improves data integrity while maintaining storage efficiency, particularly in memory cells experiencing higher error rates due to voltage distribution overlaps. The approach helps mitigate errors without unnecessary overhead, extending the lifespan of the memory system.
7. The memory system according to claim 6 , wherein the controller circuit is further configured to: change the code rate with regard to the area from the first code rate to a third code rate that is less than the second code rate, upon the condition being satisfied and the number of memory cells being above a second threshold number that is greater than the first threshold number.
The invention relates to memory systems, specifically to adaptive error correction coding in non-volatile memory to improve reliability. The problem addressed is maintaining data integrity in memory cells as they degrade over time, particularly in high-density storage where error rates increase. Traditional fixed-rate error correction codes (ECC) may either provide insufficient protection for degraded cells or waste resources on healthy cells. The memory system includes a controller circuit that dynamically adjusts the code rate (a measure of redundancy in ECC) based on the condition of memory cells. The controller monitors the number of memory cells in a given area and their error characteristics. If a condition (e.g., error rate exceeding a threshold) is met and the number of cells exceeds a first threshold, the code rate is increased from a first rate to a second, higher rate to enhance error correction. If the condition persists and the cell count further exceeds a second, higher threshold, the code rate is adjusted to a third rate, which is lower than the second rate but still higher than the initial rate. This tiered approach balances error correction strength with resource efficiency, adapting to varying levels of memory degradation. The system ensures reliable data storage while optimizing performance and storage capacity.
8. The memory system according to claim 7 , wherein the controller circuit is further configured to: invalidate the area upon determining that the number of memory cells during the read operation is above a third threshold number that is greater than the second threshold number.
A memory system includes a controller circuit that manages data storage and retrieval operations in a non-volatile memory array. The system addresses the problem of data integrity and performance degradation in memory cells that experience excessive read operations, which can lead to wear and reliability issues. The controller circuit monitors the number of read operations performed on specific memory cells or areas of the memory array. If the number of read operations exceeds a first threshold, the controller performs a data relocation operation to move the data to a different area of the memory array, thereby reducing wear on the frequently accessed cells. If the number of read operations exceeds a second threshold, which is higher than the first, the controller invalidates the area, preventing further access to the data stored there. Additionally, if the number of read operations exceeds a third threshold, which is higher than the second, the controller also invalidates the area, ensuring that heavily accessed regions are retired to maintain system reliability. This multi-tiered threshold approach allows the system to balance performance and longevity by dynamically managing memory cell usage based on read operation frequency.
9. The memory system according to claim 6 , wherein the controller circuit is further configured to: perform a threshold voltage tracking operation to determine the optimum read voltage for the read operation.
A memory system includes a non-volatile memory device and a controller circuit that manages data storage and retrieval. The system addresses challenges in accurately reading data from memory cells, particularly as the cells degrade over time due to wear and environmental factors. The controller circuit is configured to perform a threshold voltage tracking operation to determine the optimum read voltage for a read operation. This involves monitoring the threshold voltage distribution of memory cells to adjust the read voltage dynamically, ensuring reliable data retrieval even as the cells' electrical characteristics shift. The system may also include error correction mechanisms to handle data corruption and wear-leveling techniques to distribute write operations evenly across memory blocks, extending the lifespan of the memory device. The threshold voltage tracking operation helps mitigate read errors caused by variations in cell threshold voltages, improving overall system performance and data integrity. The controller circuit may further implement adaptive read schemes, such as adjusting read voltages based on historical performance data or environmental conditions, to enhance accuracy. This approach ensures that the memory system maintains high reliability and efficiency throughout its operational life.
10. A method of controlling a memory system including a memory having a plurality of areas, the method comprising: during a write operation to write data to an area among a plurality of areas, encoding first data to be written to at a first code rate; changing a code rate with regard to the area from the first code rate to a second code rate that is less than the first code rate when a condition for changing the code rate with regard to the area is satisfied; and during a next write operation to write data to the area, encoding second data to be written to the area at the second code rate, after changing the first code rate to the second code rate, wherein the condition for the changing the code rate includes: a number of erase operations processed for the area reaching a predetermined number, and a certain amount of time elapsing since programming the first data to the area.
This invention relates to memory systems, specifically to methods for dynamically adjusting error correction coding (ECC) rates in non-volatile memory to improve reliability and longevity. The problem addressed is the degradation of memory cells over time due to repeated erase/write cycles and data retention issues, which can lead to increased error rates. The solution involves dynamically changing the ECC code rate (a measure of redundancy in error correction) for specific memory areas based on usage and time factors. The method operates during write operations to a memory area. Initially, data is encoded at a first code rate (e.g., a lower redundancy rate for better storage efficiency). If a condition is met, the code rate for that area is adjusted to a second, higher redundancy rate (e.g., stronger error correction). The condition includes either the area reaching a predetermined number of erase operations or a certain time elapsing since the last write. Subsequent writes to that area then use the new, higher redundancy rate. This adaptive approach balances storage efficiency and reliability, extending the usable life of the memory by compensating for wear and retention degradation. The method is particularly useful in flash memory and other non-volatile storage systems where cell endurance and data integrity are critical.
11. The method according to claim 10 , further comprising: during a read operation to read the first data from the area before changing the code rate with regard to the area from the first code rate to the second code rate, decoding the first data read from the area at the first code rate; and changing the code rate with regard to the area from the first code rate to the second code rate, upon the condition being satisfied and the number of error bits during the read operation of the first data being above a first threshold number.
This invention relates to data storage systems, specifically methods for adjusting code rates in memory devices to improve error correction performance. The problem addressed is the need to dynamically adapt error correction coding (ECC) parameters to maintain data integrity as memory cells degrade over time. The method involves monitoring read operations in a memory area to assess data reliability. If a condition is met—such as a threshold number of read operations or a detected error rate—the system evaluates the number of error bits during a read operation. If the error bits exceed a first threshold, the code rate for that memory area is changed from a first rate to a second rate. This adjustment enhances error correction capability, compensating for increased bit errors due to wear or other factors. The method ensures data integrity by dynamically optimizing ECC parameters without requiring full memory rewrites. The approach is particularly useful in non-volatile memory systems like flash storage, where cell degradation over time necessitates adaptive error handling. The system may also include steps to verify the effectiveness of the code rate change by performing subsequent read operations and adjusting further if needed. This dynamic adaptation extends the usable lifespan of memory devices by proactively mitigating errors before they become uncorrectable.
12. The method according to claim 11 , further comprising: changing the code rate with regard to the area from the first code rate to a third code rate that is less than the second code rate, upon the condition being satisfied and the number of error bits during the read operation of the first data being above a second threshold number that is greater than the first threshold number.
This invention relates to data storage systems, specifically methods for adjusting error correction coding (ECC) parameters during read operations to improve reliability. The problem addressed is ensuring accurate data retrieval in storage systems where error rates may vary across different storage areas, such as in flash memory or other non-volatile storage media. The method involves monitoring error rates during read operations and dynamically adjusting the code rate of the ECC used for error correction. Initially, a first code rate is applied to a storage area, and if a condition is met (e.g., a detected error rate exceeds a first threshold), the code rate is changed to a second, more robust code rate. If the error rate remains high—specifically, if the number of error bits exceeds a second, higher threshold—the code rate is further adjusted to a third, even more robust code rate. This progressive adjustment ensures that areas with higher error rates receive stronger error correction, improving data integrity without unnecessarily increasing overhead in low-error areas. The method may also involve tracking error rates over multiple read operations to refine adjustments. This approach optimizes storage reliability by dynamically adapting to varying error conditions in different storage regions.
13. The method according to claim 12 , further comprising: invalidating the area upon determining that the number of error bits during the read operation is above a third threshold number that is greater than the second threshold number.
A method for managing memory storage involves detecting and handling errors during read operations. The method operates in a memory system where data is stored in memory cells, and errors may occur during read operations due to factors like wear or degradation. The method includes performing a read operation on a memory area, counting the number of error bits detected during the read, and comparing this count to predefined threshold values. If the error count exceeds a first threshold, the method triggers an error correction process to correct the detected errors. If the error count exceeds a second threshold, which is higher than the first, the method marks the memory area as requiring future maintenance, such as data relocation or retirement. Additionally, if the error count exceeds a third threshold, which is higher than the second, the method invalidates the memory area entirely, preventing further use to avoid data corruption. The method ensures reliable data storage by dynamically adjusting error handling based on the severity of detected errors, balancing between correction, maintenance, and invalidation to maintain system integrity.
14. The method according to claim 11 , further comprising: performing a threshold voltage tracking operation to determine the read voltage for the read operation.
A method for memory storage systems addresses the challenge of accurately reading data from non-volatile memory cells, particularly as the cells degrade over time. The method involves adjusting read voltages to compensate for shifts in the threshold voltages of memory cells, which can occur due to wear, temperature changes, or other environmental factors. The method includes performing a threshold voltage tracking operation to dynamically determine the optimal read voltage for a read operation. This tracking operation monitors the threshold voltage distribution of memory cells and adjusts the read voltage accordingly to ensure reliable data retrieval. The method may also involve pre-reading a subset of memory cells to estimate the threshold voltage distribution before applying the read voltage. By continuously tracking and adjusting the read voltage, the method improves read accuracy and extends the lifespan of the memory cells. This approach is particularly useful in flash memory and other non-volatile storage technologies where threshold voltage shifts can lead to read errors. The method ensures that data is read correctly even as the memory cells degrade, enhancing the overall reliability of the storage system.
15. The method according to claim 10 , wherein the area comprises a plurality of memory cells, and the method further comprises: processing a read operation to read the first data from the area before changing the code rate with regard to the area from the first code rate to the second code rate; and changing the code rate from the first code rate to the second code rate, upon the condition being satisfied and the number of memory cells having a threshold voltage within a voltage range that includes an optimum read voltage within overlapped threshold voltage distributions being above a first threshold number.
This invention relates to memory systems, specifically to methods for adjusting code rates in memory storage areas to improve data reliability. The problem addressed is maintaining data integrity in memory cells where threshold voltage distributions overlap, leading to read errors. The method involves monitoring memory cells in an area to determine if a condition is met, such as a certain number of cells having threshold voltages within a specific voltage range that includes an optimum read voltage. Before changing the code rate, the method reads the first data from the area. If the condition is satisfied and the number of memory cells with threshold voltages within the specified range exceeds a predefined threshold, the code rate is adjusted from a first rate to a second rate. This adjustment helps mitigate errors caused by overlapping threshold voltage distributions, improving data reliability. The method ensures data is read before the code rate change to prevent data loss during the transition. The invention is particularly useful in non-volatile memory systems where threshold voltage shifts over time degrade performance.
16. The method according to claim 15 , further comprising: changing the code rate with regard to the area from the first code rate to a third code rate that is less than the second code rate, upon the condition being satisfied and the number of memory cells being above a second threshold number that is greater than the first threshold number.
A method for adjusting code rates in a memory system addresses the challenge of optimizing data storage efficiency and reliability in non-volatile memory devices, particularly in scenarios where memory cells degrade over time. The method involves monitoring the condition of memory cells, such as their wear level or error rates, and dynamically adjusting the code rate—a parameter that determines the redundancy or error correction capability of the stored data. Initially, the method operates at a first code rate, which provides a baseline level of error correction. When a specific condition is met—such as a detected increase in error rates or wear—the code rate is adjusted to a second, higher code rate to enhance error correction and maintain data integrity. Additionally, if the number of memory cells exceeds a first threshold, the code rate is further adjusted to a third, lower code rate to balance between error correction and storage efficiency. This adaptive approach ensures reliable data storage while optimizing the use of memory resources, particularly in systems where memory cells are subject to varying levels of degradation. The method is applicable to solid-state drives, flash memory, and other non-volatile storage technologies where dynamic error correction is critical.
17. The method according to claim 16 , further comprising: invalidating the area upon determining that the number of memory cells during the read operation is above a third threshold number that is greater than the second threshold number.
A method for managing memory operations in a storage system addresses the problem of maintaining data integrity and performance in non-volatile memory devices, particularly when read operations may cause unintended disturbances to adjacent memory cells. The method involves monitoring the number of memory cells accessed during a read operation and comparing this count to predefined threshold values to determine whether corrective action is needed. If the number of accessed cells exceeds a first threshold, a first set of mitigation steps is triggered, such as adjusting read parameters or performing error correction. If the count exceeds a second, higher threshold, a second set of more aggressive mitigation steps is taken, such as relocating data or marking the affected area as invalid. The method further includes invalidating the area when the number of accessed cells surpasses a third, even higher threshold, ensuring that severely disturbed regions do not compromise system reliability. This approach dynamically adapts to varying levels of read-induced disturbances, balancing performance and data integrity in memory storage systems.
18. The method according to claim 15 , further comprising: performing a threshold voltage tracking operation to determine the optimum read voltage for the read operation.
This invention relates to memory systems, specifically to optimizing read operations in non-volatile memory devices. The problem addressed is the degradation of read accuracy over time due to variations in threshold voltages of memory cells, which can lead to read errors. The invention provides a method to improve read reliability by dynamically adjusting read voltages based on threshold voltage tracking. The method involves performing a threshold voltage tracking operation to determine the optimum read voltage for a read operation. This tracking operation monitors changes in the threshold voltages of memory cells, which can shift due to factors like wear, temperature, or data retention effects. By analyzing these shifts, the system calculates an optimal read voltage that minimizes read errors. The tracking operation may involve reading reference cells or performing test reads to assess voltage distributions. The determined optimum read voltage is then applied during subsequent read operations to ensure accurate data retrieval. This approach enhances read performance and reliability in memory systems, particularly in flash memory and other non-volatile storage technologies where threshold voltage variations are common. The method can be integrated into existing memory controllers or firmware to improve data integrity without requiring hardware modifications.
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September 29, 2020
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