Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A gate driving circuit, comprising: 1 st to N th stage shift registers configured to respectively provide 1 st to N th stage scan signals to 1 st to N th gate lines of a display panel, wherein N is an integer greater than or equal to 4; wherein an m th stage shift register of the 1 st to N th stage shift registers comprises an m th main circuit, an m th discharge circuit, a first node and a second node; wherein the m th main circuit comprises: an m th pre-charge unit that is coupled to the first node of the m th stage shift register and is configured to output a pre-charge signal to the first node of the m th stage shift register; an m th pull-up unit that is coupled to the first node and the second node of the m th stage shift register, and is configured to output an m th stage scan signal of the 1 st to N th stage scan signals to the second node of the m th stage shift register; and an m th reset unit that is coupled to the first node of the m th stage shift register and is configured to receive a reset signal; and the m th discharge circuit comprises: an m th pull-down unit that is coupled to the first node and the second node of the m th stage shift register, and is configured to receive one of a first pull-down control signal and a second pull-down control signal, wherein the first pull-down control signal and the second pull-down control signal are phase-inverted with respect to each other during an image display period of the display panel; wherein m is an integer that is greater than or equal to 1 and less than or equal to N; wherein an i th pull-down unit is configured to receive the first pull-down control signal, and an (i+1) th pull-down unit is configured to receive the second pull-down control signal, wherein i is an odd number greater than or equal to 1 and less than or equal to N.
A gate driving circuit for a display panel includes a series of shift registers that generate scan signals for driving gate lines. The circuit comprises first to Nth stage shift registers, where N is at least 4, each providing a corresponding scan signal to a gate line. Each shift register stage includes a main circuit and a discharge circuit, with two internal nodes. The main circuit contains a pre-charge unit that outputs a pre-charge signal to the first node, a pull-up unit that outputs the scan signal to the second node, and a reset unit that receives a reset signal. The discharge circuit includes a pull-down unit connected to both nodes, which receives either a first or second pull-down control signal. These signals are phase-inverted during the display period. The pull-down units alternate between receiving the first and second control signals, with odd-numbered stages receiving the first signal and even-numbered stages receiving the second. This design ensures stable and synchronized gate line driving by preventing signal interference between adjacent stages. The alternating control signals help maintain proper timing and reduce power consumption.
2. The gate driving circuit of claim 1 , wherein an i th main circuit is coupled to an (i+1) th discharge circuit, and an i th discharge circuit is coupled to an (i+1) th main circuit.
A gate driving circuit for power semiconductor devices, such as those used in power conversion systems, addresses the challenge of efficiently controlling multiple semiconductor switches in a cascaded or interleaved configuration. The circuit includes a plurality of main circuits and discharge circuits, where each main circuit is responsible for driving a corresponding semiconductor switch, while each discharge circuit facilitates the discharge of residual energy or voltage from the switch. The invention improves upon existing designs by ensuring that each main circuit is coupled to a subsequent discharge circuit, and each discharge circuit is coupled to a subsequent main circuit. This interconnection allows for coordinated control and energy management across the system, reducing switching losses, improving efficiency, and enhancing reliability. The arrangement ensures that energy dissipation is managed effectively, preventing voltage spikes and ensuring stable operation. The circuit is particularly useful in high-power applications where precise timing and energy management are critical, such as in inverters, converters, and motor drives. The interlinked structure of main and discharge circuits enables synchronized operation, minimizing transient effects and improving overall system performance.
3. The gate driving circuit of claim 2 , wherein the (i+1) th discharge circuit is coupled to the first node and the second node of the i th stage shift register, and the i th discharge circuit is coupled to the first node and the second node of the (i+1) th stage shift register.
This invention relates to gate driving circuits for display panels, specifically addressing the issue of signal interference and leakage in shift register circuits. The invention provides a discharge circuit configuration that reduces signal distortion and improves reliability in gate driving circuits. The gate driving circuit includes multiple stages of shift registers, each stage having a first node and a second node. The discharge circuits are strategically coupled between adjacent shift register stages to prevent signal leakage and interference. Specifically, the (i+1)th discharge circuit is connected to the first and second nodes of the ith stage shift register, while the ith discharge circuit is connected to the first and second nodes of the (i+1)th stage shift register. This cross-coupling ensures that each discharge circuit can effectively discharge residual signals from the adjacent stage, minimizing signal crosstalk and enhancing circuit stability. The discharge circuits are designed to rapidly discharge unwanted voltages from the nodes, preventing charge accumulation that could lead to incorrect signal propagation. This configuration improves the accuracy of gate driving signals, reducing display artifacts such as flickering or uneven brightness. The invention is particularly useful in high-resolution displays where precise timing and signal integrity are critical. The discharge circuits operate in synchronization with the shift register stages, ensuring efficient signal management without additional power consumption.
4. The gate driving circuit of claim 1 , wherein the m th reset unit is configured to reset a voltage level of the first node of the m th stage shift register after the gate driving circuit generates the 1 st to N th stage scan signals.
A gate driving circuit for display panels, particularly for controlling scan signals in display devices, addresses the challenge of maintaining stable voltage levels in shift registers during operation. The circuit includes multiple stages of shift registers, each generating scan signals for driving gate lines in a display. A reset unit is integrated into each stage to reset the voltage level of a control node after the circuit has generated the first to Nth stage scan signals. This reset mechanism ensures proper operation by preventing voltage drift or instability in the control node, which could otherwise lead to malfunctions in subsequent scan signal generation. The reset unit operates after the completion of the initial scan signals, ensuring that the control node is reset to a predefined level before the next cycle begins. This design improves the reliability and consistency of the gate driving circuit, particularly in large-area displays where maintaining precise voltage levels is critical for uniform display performance. The reset functionality is essential for preventing errors in scan signal timing and ensuring accurate display operation.
5. The gate driving circuit of claim 4 , wherein the m th reset unit is configured to reset the voltage level of the first node of the m th stage shift register after the gate driving circuit generates the 1 st to N th stage scan signals in a j th frame period and before the gate driving circuit generates the 1 st stage scan signals in a (j+1) th frame period, wherein j is integer that is greater than or equal to 1.
This invention relates to gate driving circuits for display panels, specifically addressing the issue of maintaining stable voltage levels in shift register stages during frame transitions. The circuit includes multiple stages of shift registers, each generating scan signals for driving gate lines in a display. A reset unit is integrated into each stage to reset the voltage level of a control node after the completion of scan signal generation in a current frame and before the start of the next frame. This reset operation ensures that the control node returns to a consistent initial state, preventing voltage drift or instability that could affect the accuracy of subsequent scan signals. The reset unit operates during the transition between consecutive frames, such as between the jth and (j+1)th frame, where j is an integer greater than or equal to 1. By resetting the control node voltage after the Nth stage scan signal is generated in the jth frame and before the 1st stage scan signal is generated in the (j+1)th frame, the circuit maintains reliable operation across multiple frames, improving display uniformity and performance. The reset mechanism is particularly useful in large-area displays where voltage fluctuations can accumulate over time.
6. The gate driving circuit of claim 1 , wherein the m th reset unit is configured to reset a voltage level of the first node of the m th stage shift register before the display panel displays a first frame after the display panel enters a display status.
A gate driving circuit for a display panel includes multiple stage shift registers, each with a first node. The circuit addresses the issue of display abnormalities, such as flickering or uneven brightness, that can occur when the display panel transitions from a non-display to a display state. Specifically, the m-th reset unit in the circuit is designed to reset the voltage level of the first node in the m-th stage shift register before the display panel begins displaying its first frame after entering the display state. This reset operation ensures stable signal output from the shift register, preventing potential malfunctions during the transition. The reset unit may include a transistor or other switching element that temporarily discharges or clamps the first node to a predetermined voltage level, such as a low voltage, to initialize the circuit before normal operation. This pre-reset step is critical for maintaining consistent display quality, particularly in applications where the panel frequently switches between active and standby modes. The circuit is commonly used in liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, where precise timing and signal integrity are essential for optimal performance.
7. The gate driving circuit of claim 1 , wherein the m th precharge unit comprises: a first transistor, wherein a control terminal of the first transistor is configured to receive a first input signal, a first terminal of the first transistor is configured to receive a first reference voltage level, and a second terminal of the first transistor is coupled to the first node of the m th stage shift register; and a second transistor, wherein a control terminal of the second transistor is configured to receive a second input signal, a first terminal of the second transistor is configured to receive a second reference voltage level, and a second terminal of the second transistor is coupled to the first node of the m th stage shift register.
This invention relates to gate driving circuits, specifically a precharge unit within a shift register stage used in display driver circuits. The problem addressed is the need for controlled precharging of a node in a shift register to ensure proper signal propagation and timing in display applications. The precharge unit is part of a shift register stage and includes two transistors. The first transistor has its control terminal connected to a first input signal, its first terminal connected to a first reference voltage level, and its second terminal coupled to a node in the shift register. The second transistor has its control terminal connected to a second input signal, its first terminal connected to a second reference voltage level, and its second terminal also coupled to the same node. The first and second reference voltage levels may be different, allowing flexible voltage control for precharging the node. The first and second input signals independently control the transistors, enabling precise timing and voltage adjustment during the precharge phase. This design ensures stable and accurate signal generation in the shift register, which is critical for driving gate lines in display panels. The precharge unit can be integrated into any shift register stage to improve reliability and performance in display driver circuits.
8. The gate driving circuit of claim 7 , wherein when m is any integer of 1 to 2, the first input signal is a starting signal, and the second input signal is an (m+3) th stage scan signal of the 1 st to N th stage scan signals; when m is any integer of 3 to (N−3), the first input signal is an (m−2) th stage scan signal of the 1 st to N th stage scan signals, and the second input signal is an (m+3) th stage scan signal of the 1 st to N th stage scan signals; when m is any integer of (N−2) to N, the first input signal is an (m−2) th stage scan signal of the 1 st to N th stage scan signals, and the second input signal is an ending signal.
The invention relates to a gate driving circuit for a display device, specifically addressing the challenge of efficiently generating scan signals in a shift register circuit. The circuit includes multiple stages, each producing a scan signal for driving gate lines in a display panel. The circuit receives a starting signal and an ending signal to initiate and terminate the scan signal generation process. For stages near the beginning (m=1 to 2), the first input signal is the starting signal, and the second input signal is a subsequent scan signal from a later stage (m+3). For intermediate stages (m=3 to N-3), the first input signal is a scan signal from a preceding stage (m-2), and the second input signal is a scan signal from a later stage (m+3). For stages near the end (m=N-2 to N), the first input signal is a scan signal from a preceding stage (m-2), and the second input signal is the ending signal. This configuration ensures proper signal propagation and synchronization across all stages, enabling reliable display operation. The circuit simplifies the design by reducing the number of external control signals required, improving efficiency and reducing power consumption.
9. The gate driving circuit of claim 7 , wherein the m th pull-up unit comprises: a third transistor, wherein a control terminal of the third transistor is coupled to the first node of the m th stage shift register, a first terminal of the third transistor is configured to receive a clock signal, and a second terminal of the third transistor is configured to output the m th stage scan signal.
This invention relates to gate driving circuits for display panels, specifically addressing the need for efficient and reliable signal transmission in shift register-based gate driving circuits. The invention improves upon prior art by enhancing the pull-up unit within a shift register stage to ensure stable and accurate output of scan signals. The gate driving circuit includes multiple shift register stages, each generating a scan signal for driving a corresponding gate line in a display panel. The m-th stage shift register includes a pull-up unit that receives a clock signal and outputs the m-th stage scan signal. The pull-up unit comprises a third transistor, where the control terminal (e.g., gate) of the third transistor is connected to the first node of the m-th stage shift register. The first terminal (e.g., source or drain) of the third transistor receives the clock signal, while the second terminal (e.g., drain or source) outputs the m-th stage scan signal. This configuration ensures that the clock signal is accurately transmitted to the output node when the first node is activated, thereby generating the scan signal with minimal distortion and delay. The invention improves signal integrity and reduces power consumption by optimizing the pull-up unit's structure and connections.
10. The gate driving circuit of claim 1 , wherein the m th reset unit comprises: a reset transistor, wherein a control terminal of the reset transistor is configured to receive the reset signal, a first terminal of the reset transistor is configured to receive a reference voltage level, and a second terminal of the reset transistor is coupled to the first node of the m th stage shift register.
A gate driving circuit for display panels, particularly for organic light-emitting diode (OLED) displays, addresses the challenge of accurately controlling gate signals to ensure proper pixel operation. The circuit includes multiple stage shift registers, each generating a gate signal for driving a row of pixels. Each stage shift register has a reset unit that resets the output node to a stable state before the next signal is generated, preventing signal interference and improving display quality. The reset unit in the m-th stage shift register comprises a reset transistor. The control terminal of this transistor receives a reset signal, which activates the transistor to reset the first node of the m-th stage shift register. The first terminal of the reset transistor is connected to a reference voltage level, which sets the voltage at the first node when the transistor is activated. The second terminal of the reset transistor is coupled to the first node of the m-th stage shift register, ensuring that the node is reset to the reference voltage level when the reset signal is applied. This reset operation is critical for maintaining signal integrity and preventing carry-over effects between consecutive gate signals, thereby enhancing the reliability and performance of the display panel. The reset transistor operates in response to the reset signal, ensuring precise timing and synchronization with other circuit operations.
11. A display panel having a display area and a non-display area, the display panel comprising: a substrate; 1 st to N th gate lines disposed on the substrate and in the display area; a first gate driving circuit disposed on the substrate and in the non-display area, the first gate driving circuit comprising 1 st to N th stage shift registers that are configured to respectively provide 1 st to N th stage first scan signals to the 1 st to N th gate lines in the display area, wherein N is an integer greater than or equal to 4; and a first reset signal line disposed on the substrate and in the non-display area, the first reset signal line coupled to the 1 st to N th stage shift registers; wherein an m th stage shift register of the 1 st to N th stage shift registers comprises an m th main circuit, an m th discharge circuit and a wiring; wherein the m th main circuit comprises: an m th pre-charge unit that is coupled to a first node of the m th stage shift register and is configured to output a pre-charge signal to the first node of the m th stage shift register, the m th precharge unit comprising: a first transistor that is configured to receive a first input signal, and is coupled to the first node of the m th stage shift register; and a second transistor that is configured to receive a second input signal, and is coupled to the first node of the m th stage shift register; an m th pull-up unit that is coupled to the first node and a second node of the m th stage shift register and is configured to output an m th stage first scan signal of the 1 st to N th stage first scan signals to the second node of the m th stage shift register, the m th pull-up unit comprising: a third transistor that is coupled to the first node and the second node of the m th stage shift register, and is configured to receive a clock signal and output the m th first scan signal; and an m th reset unit that is coupled to the first node of the m th stage shift register, wherein the first reset signal line is configured to provide a reset signal to the m th reset unit, the m th reset unit comprising: a reset transistor that is coupled to the first node of the m th stage shift register and is configured to receive the reset signal, wherein the reset transistor is disposed between the second transistor and the third transistor; and the m th discharge circuit comprises: an m th pull-down unit that is coupled to the first node and the second node of the m th stage shift register and is configured to receive a pull-down control signal; wherein m is an integer that is greater than or equal to 1 and less than or equal to N; wherein the wiring of the m th stage shift register is disposed between the reset signal line and a control terminal of the reset transistor of the m th stage shift register and is electrically connected to the first reset signal line and the control terminal of the reset transistor of the m th stage shift register, and the wiring of the m th stage shift register and the first reset signal line are formed from different metal layers.
A display panel includes a display area with gate lines and a non-display area containing a gate driving circuit. The gate driving circuit comprises multiple stage shift registers that generate scan signals for the gate lines. Each shift register stage includes a main circuit and a discharge circuit. The main circuit has a pre-charge unit with two transistors receiving input signals, a pull-up unit with a transistor outputting a scan signal based on a clock signal, and a reset unit with a reset transistor controlled by a reset signal line. The reset transistor is positioned between the pre-charge and pull-up transistors. The discharge circuit includes a pull-down unit that receives a pull-down control signal. A wiring connects the reset signal line to the reset transistor's control terminal, with the wiring and reset signal line formed from different metal layers. This design ensures proper signal transmission and reset functionality in the gate driving circuit, improving display panel performance. The structure allows for efficient signal control and reduces interference between components.
12. The display panel of claim 11 , wherein an i th main circuit is coupled to an (i+1) th discharge circuit, and an i th discharge circuit is coupled to an (i+1) th main circuit, wherein i is an odd number greater than or equal to 1 and less than or equal to N.
This invention relates to display panel circuitry, specifically addressing the challenge of efficiently managing electrical discharge in display panels to improve performance and reliability. The display panel includes multiple main circuits and discharge circuits arranged in a cascaded configuration. Each main circuit is connected to a subsequent discharge circuit, and each discharge circuit is connected to a subsequent main circuit. The connections follow a specific pattern where an i-th main circuit is coupled to an (i+1)-th discharge circuit, and an i-th discharge circuit is coupled to an (i+1)-th main circuit. The variable i is an odd integer ranging from 1 to N, ensuring a structured and alternating connection sequence between the main and discharge circuits. This arrangement facilitates controlled discharge of electrical energy, reducing the risk of voltage spikes and improving the stability of the display panel. The cascaded design ensures efficient energy management while maintaining the integrity of the display's electrical components. The invention is particularly useful in high-resolution or high-brightness displays where precise control of electrical discharge is critical for optimal performance.
13. The display panel of claim 11 , wherein the first reset signal line is disposed between the display area and the 1 st to N th stage shift registers.
A display panel includes a display area with multiple pixels and a gate driver circuit integrated on the same substrate. The gate driver circuit has a plurality of stage shift registers connected in series, each generating a scan signal to drive the pixels. The display panel also includes a first reset signal line that provides a reset signal to the stage shift registers. This reset signal line is positioned between the display area and the stage shift registers, ensuring proper signal transmission and minimizing interference. The arrangement helps maintain signal integrity and reduces layout complexity. The display panel may also include additional reset signal lines for further control, such as a second reset signal line connected to the first stage shift register. The gate driver circuit may operate in a forward or backward scanning mode, with the reset signal line adjusting accordingly to maintain stable operation. This design improves the reliability and performance of the integrated gate driver circuit in the display panel.
14. The display panel of claim 11 , further comprising: a second gate driving circuit and a second reset signal line disposed on the substrate and in the non-display area, the first gate driving circuit and the second gate driving circuit disposed respectively at two opposite sides of the display panel, and the first reset signal line and the second reset signal line disposed respectively at two opposite sides of the display panel; wherein the first gate driving circuit and the second gate driving circuit have the same circuit, the second reset signal line is coupled to 1 st to N th stage shift registers of the second gate driving circuit, and the second gate driving circuit is configured to provide 1 st to N th stage second scan signals to the 1 st to N th gate lines; wherein one end and the other end of each of the 1 st to N th gate lines are respectively coupled to the first gate driving circuit and the second gate driving circuit, and waveforms and time sequences of the 1 st to N th stage first scan signals are respectively the same as waveforms and time sequences of the 1 st to N th stage second scan signals.
This invention relates to a display panel with dual gate driving circuits and reset signal lines for improved display performance. The display panel includes a substrate with a display area and a non-display area. A first gate driving circuit and a first reset signal line are disposed in the non-display area on one side of the panel. A second gate driving circuit and a second reset signal line are disposed in the non-display area on the opposite side of the panel. Both gate driving circuits have identical circuitry and are configured to provide scan signals to gate lines. Each gate line is connected at one end to the first gate driving circuit and at the other end to the second gate driving circuit. The first reset signal line is coupled to the first gate driving circuit, while the second reset signal line is coupled to the second gate driving circuit. The scan signals generated by both gate driving circuits have identical waveforms and timing sequences. This dual-circuit configuration ensures synchronized signal transmission across the display panel, reducing signal delay and improving display uniformity. The reset signal lines help maintain proper circuit operation by resetting the gate driving circuits as needed. This design is particularly useful for large-area displays where signal integrity and synchronization are critical.
15. A gate driving circuit, comprising: 1 st to N th stage shift registers configured to respectively provide 1 st to N th stage scan signals to 1 st to N th gate lines of a display panel, wherein N is an integer greater than or equal to 4; wherein an i th stage shift register of the 1 st to N th stage shift registers comprises an i th main circuit and an i th discharge circuit, an (i+1) th stage shift register of the 1 st to N th stage shift registers comprises an (i+1) th main circuit and an (i+1) th discharge circuit, the i th main circuit is coupled to the i th discharge circuit and the (i+1) th discharge circuit, and the (i+1) th main circuit is coupled to the i th discharge circuit and the (i+1) th discharge circuit; wherein the i th main circuit comprises: an i th pre-charge unit that is coupled to a first node of the i th stage shift register and is configured to output an i th pre-charge signal to the first node of the i th stage shift register; an i th pull-up unit that is coupled to the first node and a second node of the i th stage shift register and is configured to output an i th stage scan signal of the 1 st to N th stage scan signals to the second node of the i th stage shift register; and an i th reset unit that is configured to receive the reset signal and is coupled to the first node of the i th reset unit; wherein the (i+1) th main circuit comprises: an (i+1) th pre-charge unit that is coupled to a first node of the (i+1) th stage shift register and is configured to output an (i+1) th pre-charge signal to the first node of the (i+1) th stage shift register; and an (i+1) th pull-up unit that is coupled to the first node and a second node of the (i+1) th stage shift register and is configured to output an (i+1) th stage scan signal of the 1 st to N th stage scan signals to the second node of the (i+1) th stage shift register; and an (i+1) th reset unit that is configured to receive the reset signal and is coupled to the first node of the (i+1) th reset unit; wherein i is an odd number greater than or equal to 1 and less than or equal to N; wherein the i th discharge circuit is coupled to the first node and the second node of the i th main circuit and the first node and the second node of the (i+1) th main circuit, and the (i+1) th discharge circuit is coupled to the first node and the second node of the i th main circuit, and the first node and the second node of the (i+1) th main circuit.
A gate driving circuit for display panels includes multiple cascaded shift registers that generate scan signals for driving gate lines. Each shift register stage comprises a main circuit and a discharge circuit. The main circuit includes a pre-charge unit, a pull-up unit, and a reset unit. The pre-charge unit outputs a pre-charge signal to a first node, the pull-up unit generates a scan signal at a second node, and the reset unit receives a reset signal to control the first node. The discharge circuit is connected to both the current and subsequent shift register stages, ensuring proper signal discharge and preventing signal interference. The circuit is designed to improve signal stability and reduce power consumption by efficiently managing charge and discharge operations across adjacent stages. The configuration ensures reliable scan signal generation for display panel operation, particularly in large-screen applications where multiple gate lines require precise timing control. The discharge circuits are interconnected between consecutive stages to maintain signal integrity and minimize leakage currents.
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January 5, 2021
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