Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a digital electronic component configured to produce a clock signal; a first counter configured to output a first count signal based on the clock signal; a second counter configured to output a second count signal based on the clock signal; and a power on reset logic configured to provide a power on reset signal based on the first count signal and the second count signal, wherein the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power; wherein the power on reset logic is configured to generate the power on reset signal upon determining: that the first counter has counted to a first pre-determined value, that the first counter has reset the second counter to a second value, that the first counter has counted to the second value, and that a difference between a value of the first counter and a value of the second counter equals a pre-determined value at a point in time that the first counter has counted to the second value.
A digital circuit includes a clock signal generator, a first counter, a second counter, and power-on reset logic. The clock signal generator provides a clock signal. The first counter counts clock cycles and outputs a first count. The second counter also counts clock cycles and outputs a second count. The power-on reset logic monitors the first and second counts. When the first counter reaches a first preset value, it resets the second counter to a specific second value. Then, after the first counter reaches the second value, the power-on reset logic calculates the difference between the first and second counts. If the difference matches a predetermined value at that point in time, the power-on reset logic generates a power-on reset signal, then disables the clock signal generator to save power.
2. The apparatus of claim 1 , wherein the apparatus is a digital electronic circuit.
The digital circuit described in claim 1 is a digital electronic circuit. This means the power-on reset circuit, the clock signal generator, the counters, and the reset logic are all part of a single integrated circuit or chip. The function is to generate a power-on reset signal when the power is turned on, and then to disable the clock to save power. The disabling happens only after a certain amount of time has elapsed, tracked by the digital counters. The circuit operates automatically upon power being applied.
3. The apparatus of claim 1 , wherein the digital electronic component includes a ring oscillator.
The digital circuit described in claim 1 uses a ring oscillator as the clock signal generator. The ring oscillator produces the clock signal that drives the first and second counters. The counters generate count signals. The power on reset logic provides a power on reset signal based on the first and second count signals. The power on reset logic is configured to disable the ring oscillator after providing the power on reset signal to prevent the ring oscillator from drawing power.
4. The apparatus of claim 1 , wherein the first counter includes a digital electronic counter configured to count clock edges in the clock signal.
The digital circuit described in claim 1 has a first counter that increments its count on each rising or falling edge of the clock signal. It is configured to count clock edges in the clock signal. This allows precise measurement of the time elapsed since power-on. The power on reset logic uses this time measurement (represented by the first counter value) to determine when to generate the power-on reset signal and disable the clock signal generator.
5. The apparatus of claim 1 , wherein the second counter includes a digital electronic counter configured to count clock edges in the clock signal.
The digital circuit described in claim 1 has a second counter that increments its count on each rising or falling edge of the clock signal. It is configured to count clock edges in the clock signal. Like the first counter, this allows precise measurement of the time elapsed since power-on or since being reset by the first counter. The power on reset logic uses the value of the second counter, in combination with the value of the first counter, to determine when to generate the power-on reset signal.
6. A circuit comprising: a digital electronic component configured to produce a clock signal, wherein the digital electronic component is connected to an input voltage; at least two counters configured to output at least two count signals based on the clock signal, wherein the at least two count signals comprise a first count signal generated from a first counter and a second count signal generated from a second counter; and a power on reset logic configured to determine a difference between a value of the first count signal and a value of the second count signal; wherein the power on reset logic is configured to provide a power on reset signal after the difference between the at least two count signals meet a pre-defined condition; wherein the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power from the input voltage after the power on reset signal is provided; and wherein the pre-defined condition is determined from: a first comparison component configured to provide a first comparison signal upon determining that the first count signal equals a first preset value, where the first comparison signal causes the second counter to be reset; a second comparison component configured to provide a second comparison signal upon determining that the first count signal equals a second preset value; and a third comparison component configured to provide a third comparison signal upon determining that the difference between the first count signal and the second count signal equals a difference between the first preset value and the second preset value, wherein the third comparison signal is used to determine if the pre-determined condition has been met.
A digital circuit includes a clock signal generator, two counters, and power-on reset logic. The clock signal generator is powered by an input voltage and produces a clock signal. The counters generate two count signals based on the clock signal. The power-on reset logic calculates the difference between the two count signals. If this difference meets a predefined condition, the power-on reset logic generates a power-on reset signal and disables the clock signal generator to save power. The predefined condition is based on three comparison components: the first compares the first count signal to a first preset value to reset the second counter. The second compares the first count signal to a second preset value. The third compares the difference between first and second count signals to the difference between the first and second preset values.
7. The circuit of claim 6 , wherein: the first counter is configured to output the first count signal based on counting edges in the clock signal, wherein the first counter is configured to begin counting at a first count value; and the second counter is configured to output the second count signal based on counting the edges in the clock signal, wherein the second counter is configured to begin counting at a second count value.
In the digital circuit described in claim 6, the first counter starts counting from a first initial value and increments its count on each edge of the clock signal. The second counter starts counting from a second initial value and also increments its count on each edge of the clock signal. The power on reset logic uses these counters and their initial values to produce a reset signal once a certain condition is met.
8. The circuit of claim 6 , wherein the digital electronic component includes a ring oscillator configured to produce the clock signal when the input voltage is at a pre-determined level.
In the digital circuit described in claim 6, the clock signal generator is a ring oscillator. The ring oscillator starts oscillating and generating the clock signal when the input voltage reaches a certain level. This enables the power-on reset circuit to function automatically as soon as sufficient power is available. The circuit will then disable the ring oscillator to save power after a reset signal has been generated.
9. The circuit of claim 6 , wherein the power on reset logic is configured to determine the pre-defined condition based on a relationship between values of the at least two count signals.
In the digital circuit described in claim 6, the power-on reset logic determines when to generate the power-on reset signal based on the relationship between the values of the two counters. It's the difference between the counts, or some other mathematical relationship between the first and second count signals, that triggers the power-on reset signal and the subsequent disabling of the clock signal generator.
10. The circuit of claim 6 , wherein the circuit being embodied in an application specific integrated circuit.
A circuit is provided for use in an application-specific integrated circuit (ASIC) to address challenges in signal processing, data conversion, or computational tasks. The circuit includes a configurable processing element capable of performing arithmetic, logic, or memory operations, with programmable parameters to adapt its functionality. It integrates a data path for handling input and output signals, along with control logic to manage operation modes and timing. The circuit may also include memory elements for storing intermediate or final results, and interfaces for communication with external components. By being implemented in an ASIC, the circuit achieves high performance, low power consumption, and compact size, making it suitable for specialized applications such as digital signal processing, cryptography, or embedded systems. The ASIC embodiment ensures optimized performance for the specific tasks it is designed to handle, reducing the need for general-purpose processing resources. The circuit's design allows for efficient execution of repetitive or computationally intensive operations, improving overall system efficiency.
11. A method comprising: generating a clock signal with a digital electronic component that is connected to an input voltage; outputting, using at least two counters, at least a first count value and a second count value based on the clock signal; determining a difference between the first count value and the second count value to determine if the difference meets a pre-defined condition; providing a power on reset signal after the difference between the first count value and the second count value meets the pre-defined condition; disabling the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power from the input voltage after the power on reset signal is provided; controlling one or more counters, in addition to the at least two counters, to be reset to a known value upon determining that a first counter of the at least two counters has reached a first pre-determined value in response to analyzing the clock signal; and wherein the power on reset signal is provided upon determining that the first counter has reached a second pre-determined value after reaching the first pre-determined value and that the first counter has reached a third pre-determined value after reaching the second pre-determined value.
A power-on reset method involves generating a clock signal, using two counters to output count values based on the clock signal, and calculating the difference between the count values. If the difference meets a predefined condition, a power-on reset signal is provided. After the power-on reset signal is provided, the clock signal generator is disabled to save power. Additional counters are reset to known values when a first counter reaches a first preset value. The power-on reset signal is provided only after the first counter reaches the first, second, and third preset values, in that sequence.
12. The method of claim 11 , wherein determining if the difference between the first count value and the second count value meets the pre-defined condition includes comparing the first count value and the second count value to identify the pre-defined condition determined from a relationship between values of the first count value and the second count value.
In the method described in claim 11, determining if the difference between the two counter values meets a predefined condition includes comparing the values to identify the condition that is determined from a relationship between these values. The method is to compare the first and second count values to pre-defined values in order to determine if the power-on reset condition is met.
13. The method of claim 11 , further comprising turning off the at least two counters after the power on reset signal is provided to prevent the at least two counters from drawing power from the input voltage.
The power-on reset method described in claim 11 includes turning off the first and second counters after the power-on reset signal is provided. This prevents the counters from drawing any further power from the input voltage. This optimization further reduces power consumption of the device by ensuring that all unnecessary components are disabled after the reset signal has been generated.
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August 19, 2014
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