Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method comprising: reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof; abstracting, through the processor, partitions of the electronic circuit based on at least one functionality thereof as part of the verification of the design; grouping, through the processor, circuit elements of the electronic circuit under each partition based on at least one of type and size thereof as part of the verification; extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the circuit elements of the electronic circuit in the design; and executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
A method for verifying electronic circuit designs uses a computer to read the circuit design, then divides the circuit into sections based on their functionality. Circuit elements within each section are grouped by type and size. The method then extracts an optimized set of instructions from a test algorithm, ensuring these instructions cover the maximum amount of logic within the circuit elements. Finally, the test algorithm is executed using only the optimized instructions, reducing the time needed to verify the circuit's design.
2. The method of claim 1 , comprising providing the test algorithm as at least one of: part of an electronic design verification tool executing on the computing device; and part of a Built-In Self Test (BIST) of at least one circuit element of the electronic circuit.
The method for verifying electronic circuit designs, as described in the previous claim, uses a test algorithm that is either part of an electronic design verification software running on the computer or part of a Built-In Self Test (BIST) embedded within at least one circuit element of the electronic circuit.
3. The method of claim 2 , further comprising, as part of the verification, at least one of: implementing a local BIST controller in each clock domain of the electronic circuit; incorporating multiple clock domains within each partition of the electronic circuit; grouping at least one circuit element under a single clock domain into the local BIST controller; implementing at least one BIST engine to be controlled by the local BIST controller based on the type of the at least one circuit element grouped thereinto; generating March Element (ME) instructions through the local BIST controller to be decoded by the at least one BIST engine; and utilizing the ME instructions to select a sequence of operations to be applied to the at least one circuit element under test.
Expanding on the electronic circuit verification method using a test algorithm as part of either an electronic design verification software or a Built-In Self Test (BIST) embedded within at least one circuit element of the electronic circuit: the verification process further includes implementing a local BIST controller in each clock domain of the circuit. Multiple clock domains can be grouped within a partition, and circuit elements under a single clock domain are grouped into the local BIST controller. A BIST engine, controlled by the local BIST controller, is implemented based on the type of circuit elements. March Element (ME) instructions are generated to select a sequence of operations to be applied to the circuit elements under test.
4. The method of claim 3 , further comprising trimming, through the at least one BIST engine, the ME instructions to dispense with redundant ME instructions based on checking at least one of: at least one functionality associated with the at least one BIST engine and at least one functionality associated with the local BIST controller.
Continuing the electronic circuit verification method described above, the BIST engine trims the ME instructions, removing redundant ones. This trimming is based on checking the functionality of the BIST engine and the local BIST controller. By removing unnecessary instructions, the verification process is further optimized for speed and efficiency.
5. The method of claim 3 , further comprising: trimming, through the at least one BIST engine, the ME instructions during decoding thereof; mimicking a behavior of the at least one BIST engine in a virtual environment; and walking through the test algorithm solely relevant to the trimmed ME instructions utilizing the local BIST controller without actual execution thereof on the at least one circuit element under test.
Extending the electronic circuit verification method using BIST, the method further includes trimming ME instructions by the BIST engine during decoding. It simulates the BIST engine's behavior in a virtual environment and walks through the test algorithm using the trimmed ME instructions and the local BIST controller, without running the tests on the actual circuit elements. This allows for preliminary validation and debugging before hardware execution.
6. The method of claim 5 , further comprising comparing a value of a decoded ME instruction with an expected value thereof through the at least one BIST engine to detect a mismatch therein.
Building on the virtual simulation of the BIST engine and trimmed ME instructions, the method also compares the decoded ME instruction value with its expected value. This comparison helps detect any mismatches, enabling early identification of errors and improving the reliability of the electronic circuit verification process.
7. The method of claim 3 , further comprising at least one of: selecting at least one memory of the electronic circuit as the at least one circuit element; and utilizing connectivity descriptors of the circuit elements of the electronic circuit in the test algorithm for optimization thereof.
Further describing the electronic circuit verification method using BIST, at least one memory component of the electronic circuit can be selected as a circuit element to be tested. Also, the connectivity descriptors of the circuit elements are used within the test algorithm for optimization, ensuring thorough testing and efficient resource allocation.
8. A computing device comprising: a memory; and a processor communicatively coupled to the memory, the processor being configured to execute instructions to: read a design of an electronic circuit as part of verification thereof, abstract partitions of the electronic circuit based on at least one functionality thereof as part of the verification of the design, group circuit elements of the electronic circuit under each partition based on at least one of type and size thereof as part of the verification, extract a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the circuit elements of the electronic circuit in the design, and execute the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
A computing device performs electronic circuit design verification. It contains memory and a processor. The processor reads the electronic circuit design, divides the circuit into sections based on functionality, and groups circuit elements within each section by type and size. The processor then extracts an optimized instruction set from a test algorithm, covering the maximum amount of logic within the circuit. Finally, the processor executes the test algorithm using only the optimized instructions, reducing the time needed for circuit design verification.
9. The computing device of claim 8 , wherein the test algorithm is provided as at least one of: part of an electronic design verification tool executing on the computing device, and part of a BIST of at least one circuit element of the electronic circuit.
The computing device described for verifying electronic circuit designs uses a test algorithm that is either part of an electronic design verification software running on the computing device or part of a Built-In Self Test (BIST) of at least one circuit element of the electronic circuit.
10. The computing device of claim 9 , wherein the processor is further configured to execute instructions as part of the verification to at least one of: implement a local BIST controller in each clock domain of the electronic circuit, incorporate multiple clock domains within each partition of the electronic circuit, group at least one circuit element under a single clock domain into the local BIST controller, implement at least one BIST engine to be controlled by the local BIST controller based on the type of the at least one circuit element grouped thereinto, generate ME instructions through the local BIST controller to be decoded by the at least one BIST engine, and utilize the ME instructions to select a sequence of operations to be applied to the at least one circuit element under test.
Expanding on the computing device that verifies electronic circuits with the test algorithm residing in electronic design verification software or a Built-In Self Test (BIST) of at least one circuit element of the electronic circuit: the processor further implements a local BIST controller in each clock domain of the circuit. Multiple clock domains can be grouped within a partition, and circuit elements under a single clock domain are grouped into the local BIST controller. A BIST engine is implemented, controlled by the local BIST controller, based on the type of circuit elements. March Element (ME) instructions are generated to select a sequence of operations to be applied to the circuit elements under test.
11. The computing device of claim 10 , wherein the processor is further configured to execute instructions to trim, through the at least one BIST engine, the ME instructions to dispense with redundant ME instructions based on checking at least one of: at least one functionality associated with the at least one BIST engine and at least one functionality associated with the local BIST controller.
Extending the computing device performing BIST-based circuit verification, the processor further trims ME instructions using the BIST engine, removing redundant ones. This trimming is based on checking the functionalities of both the BIST engine and the local BIST controller, thereby optimizing the verification process.
12. The computing device of claim 10 , wherein the processor is further configured to execute instructions to: trim, through the at least one BIST engine, the ME instructions during decoding thereof, mimic a behavior of the at least one BIST engine in a virtual environment, and walk through the test algorithm solely relevant to the trimmed ME instructions utilizing the local BIST controller without actual execution thereof on the at least one circuit element under test.
Further describing the computing device performing BIST-based circuit verification, the processor is configured to trim ME instructions through the BIST engine during decoding, simulate the BIST engine's behavior in a virtual environment, and walk through the test algorithm using the trimmed ME instructions and the local BIST controller, without actual execution on the circuit elements. This allows for efficient preliminary validation and debugging.
13. The computing device of claim 12 , wherein the processor is further configured to execute instructions to compare a value of a decoded ME instruction with an expected value thereof through the at least one BIST engine to detect a mismatch therein.
Building on the computing device's virtual simulation of the BIST engine and trimmed ME instructions, the processor also compares a decoded ME instruction value with its expected value. This comparison helps detect any mismatches, enabling early identification of errors and improving verification reliability.
14. The computing device of claim 10 , wherein the processor is further configured to execute instructions to: select at least one memory of the electronic circuit as the at least one circuit element, and utilize connectivity descriptors of the circuit elements of the electronic circuit in the test algorithm for optimization thereof.
Continuing the description of the computing device performing BIST-based circuit verification, the processor can select at least one memory component of the electronic circuit as a circuit element to be tested. Additionally, the processor uses connectivity descriptors of the circuit elements within the test algorithm for optimization, ensuring thorough testing and efficient resource allocation.
15. A non-transitory medium, readable through a computing device and including instructions embodied therein that are executable through the computing device, comprising: instructions to read, through a processor of the computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof; instructions to abstract, through the processor, partitions of the electronic circuit based on at least one functionality thereof as part of the verification of the design; instructions to group, through the processor, circuit elements of the electronic circuit under each partition based on at least one of type and size thereof as part of the verification; instructions to extract, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the circuit elements of the electronic circuit in the design; and instructions to execute, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
A non-transitory computer-readable medium stores instructions for electronic circuit design verification. These instructions cause the computer to read the circuit design, divide the circuit into sections based on functionality, and group circuit elements within each section by type and size. The instructions also direct the computer to extract an optimized instruction set from a test algorithm, covering the maximum amount of logic. Finally, the instructions execute the test algorithm using only the optimized instructions, reducing the time needed for circuit design verification.
16. The non-transitory medium of claim 15 , comprising instructions to provide the test algorithm as at least one of: part of an electronic design verification tool executing on the computing device; and part of a BIST of at least one circuit element of the electronic circuit.
The non-transitory computer-readable medium containing instructions for electronic circuit design verification, as described in the previous claim, provides instructions for the test algorithm to be part of an electronic design verification software running on the computing device or part of a Built-In Self Test (BIST) of at least one circuit element of the electronic circuit.
17. The non-transitory medium of claim 16 , further comprising, as part of the verification, at least one of: instructions to implement a local BIST controller in each clock domain of the electronic circuit; instructions to incorporate multiple clock domains within each partition of the electronic circuit; instructions to group at least one circuit element under a single clock domain into the local BIST controller; instructions to implement at least one BIST engine to be controlled by the local BIST controller based on the type of the at least one circuit element grouped thereinto; instructions to generate ME instructions through the local BIST controller to be decoded by the at least one BIST engine; and instructions to utilize the ME instructions to select a sequence of operations to be applied to the at least one circuit element under test.
Expanding on the non-transitory computer-readable medium containing instructions for electronic circuit design verification using a test algorithm within electronic design verification software or a Built-In Self Test (BIST) of at least one circuit element of the electronic circuit, the instructions further include implementing a local BIST controller in each clock domain of the circuit. Multiple clock domains can be grouped within a partition. Circuit elements under a single clock domain are grouped into the local BIST controller. A BIST engine is implemented and controlled by the local BIST controller, based on the type of circuit element. March Element (ME) instructions are generated to select a sequence of operations applied to the circuit elements under test.
18. The non-transitory medium of claim 17 , further comprising instructions to trim, through the at least one BIST engine, the ME instructions to dispense with redundant ME instructions based on checking at least one of: at least one functionality associated with the at least one BIST engine and at least one functionality associated with the local BIST controller.
Extending the non-transitory computer-readable medium containing instructions for BIST-based circuit verification, the instructions further direct the computer to trim ME instructions using the BIST engine, removing redundant ones. This trimming is based on checking the functionalities of both the BIST engine and the local BIST controller, optimizing the verification.
19. The non-transitory medium of claim 17 , further comprising: instructions to trim, through the at least one BIST engine, the ME instructions during decoding thereof; instructions to mimic a behavior of the at least one BIST engine in a virtual environment; and instructions to walk through the test algorithm solely relevant to the trimmed ME instructions utilizing the local BIST controller without actual execution thereof on the at least one circuit element under test.
Further describing the non-transitory computer-readable medium containing instructions for BIST-based circuit verification, the instructions also include trimming ME instructions by the BIST engine during decoding, simulating the BIST engine's behavior in a virtual environment, and walking through the test algorithm using the trimmed ME instructions and the local BIST controller, without running it on actual circuit elements.
20. The non-transitory medium of claim 19 , further comprising instructions to compare a value of a decoded ME instruction with an expected value thereof through the at least one BIST engine to detect a mismatch therein.
Building on the non-transitory computer-readable medium's virtual simulation of the BIST engine and trimmed ME instructions, the instructions also include comparing a decoded ME instruction value with its expected value. This comparison detects mismatches, enabling early error identification and improving verification reliability.
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August 19, 2014
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