Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. Apparatus for aligning data write and read operations between different buffers, the apparatus comprising: a master logic circuit configured to, based on a control signal, assert a read clock stop signal and generate a write reset enable signal from the read clock stop signal; a plurality of first-in, first-out (FIFO) buffers coupled to the master logic circuit, wherein each of the plurality of FIFO buffers comprises: a local buffer configured to i) accept write data in accordance with a write pointer and a write clock, and ii) provide data based on a read pointer and a read clock, the local buffer placed in a suspended state when the master logic circuit asserts the read clock stop signal, a local logic circuit configured to generate i) a write pointer reset signal based on the read clock stop signal and the write reset enable signal, and ii) a read pointer reset signal based on the presence of the read clock stop signal and a predefined input value, write pointer logic configured to generate and update the write pointer based on the write clock, wherein, based on a presence of the write pointer reset signal, the write pointer logic suspends movement of the write pointer, and read pointer logic configured to generate and update the read pointer based on the read clock, wherein, based on a presence of the read pointer reset signal, the read pointer logic suspends movement of the write pointer; wherein, when the master logic circuit asserts the read clock stop signal, each of the plurality of FIFO buffers suspends movement of each write pointer and each read pointer, and, when the master logic circuit de-asserts the read clock signal, each of the plurality of FIFO buffers enables movement of each write pointer, then the read pointer to align data write and read operations of the plurality of FIFO buffers.
An apparatus aligns data write and read operations between multiple FIFO buffers. A master logic circuit, upon receiving a control signal, stops the read clock shared by all FIFO buffers by asserting a "read clock stop signal" and generates a write reset enable signal from the read clock stop signal. Each FIFO buffer temporarily halts its write and read pointers when the "read clock stop signal" is active, placing the local buffer in a suspended state. A local logic circuit in each FIFO generates write and read pointer reset signals based on the read clock stop signal. When the "read clock stop signal" is removed, each FIFO restarts its write and read pointer operations, aligning the data flow across all buffers.
2. The apparatus of claim 1 , wherein when the master logic circuit de-asserts the read clock signal, each of the plurality of FIFO buffers enables movement of each read pointer with a predetermined delay from enablement of the write pointer.
The apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment) includes a feature where, after the read clock signal is de-asserted, the read pointer enablement is delayed by a specific amount of time after the write pointer is enabled. This predetermined delay after the write pointer, helps ensure proper data synchronization.
3. The apparatus of claim 1 , wherein the master logic circuit comprises a first latch module timed with the read clock and a second latch module timed with the write clock, each of the first and the second latch modules enabled based on the read clock stop signal, wherein: the first latch module is configured to latch a predefined value based on the a predefined number of cycles of the read clock and provide the predefined value to the second latch module; and the second latch module is configured to latch the output value of the first latch module based on a predefined number of cycles of the write clock and provide the write reset signal.
The apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment) comprises the master logic circuit that uses a first latch module synchronized with the read clock, and a second latch module synchronized with the write clock, both enabled by the read clock stop signal. The first latch module captures a predefined value for a set number of read clock cycles and passes it to the second latch. The second latch module then captures this value based on a number of write clock cycles and produces the write reset signal.
4. The apparatus of claim 1 , wherein, when the master logic circuit asserts the read clock stop signal, operation of the read clock is suspended, while operation of the write clock is free running.
The apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment) operates such that when the master logic asserts the read clock stop signal, the read clock is paused, while the write clock continues to run uninterrupted. This asynchronous clock behavior allows the write operations to continue while the read operations are paused for alignment.
5. The apparatus of claim 1 , wherein the local logic circuit comprises a latch configured to generate the write pointer reset signal as the write reset enable signal after a predetermined number of cycles of the write clock, and a read pointer reset signal based on the read clock stop signal.
In the apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), the local logic circuit contains a latch that generates the write pointer reset signal using the write reset enable signal after a specified number of write clock cycles. It also generates the read pointer reset signal directly from the read clock stop signal.
6. The apparatus of claim 1 , wherein the local logic circuit comprises a plurality of latches configured to generate the read pointer reset signal after a predetermined number of cycles of the read clock.
In the apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), the local logic circuit utilizes multiple latches to generate the read pointer reset signal. These latches introduce a delay, generating the reset signal after a predefined number of read clock cycles.
7. The apparatus of claim 1 , wherein the apparatus is embodied in a Serializer-Deserializer (SerDes) device.
The apparatus that aligns data write and read operations between multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment) is implemented within a Serializer-Deserializer (SerDes) device, a common component for high-speed data transmission and reception.
8. A method of aligning data write and read operations of a plurality of first-in, first-out (FIFO) buffers, the method comprising: asserting, by a master logic circuit based on a control signal, a read clock stop signal and generating a write reset enable signal from the read clock stop signal; accepting, by a local buffer, write data in accordance with a write pointer and a write clock, and providing data based on a read pointer and a read clock, the local buffer placed in a suspended state when the master logic circuit asserts the read clock stop signal, generating, by a local logic circuit, i) a write pointer reset signal based on the read clock stop signal and the write reset enable signal, and ii) a read pointer reset signal based on the presence of the read clock stop signal and a predefined input value, generating and updating, by write pointer logic, the write pointer based on the write clock, and suspending, based on a presence of the write pointer reset signal, movement of the write pointer, and generating and updating, by read pointer logic, the read pointer based on the read clock, and suspending, based on a presence of the read pointer reset signal, movement of the write pointer; wherein, when the asserting of the read clock stop signal, each of the plurality of FIFO buffers suspends movement of each write pointer and each read pointer, and, when de-asserting the read clock signal, each of the plurality of FIFO buffers enables movement of each write pointer, then the read pointer, aligning data write and read operations of the plurality of FIFO buffers.
A method aligns data write/read operations across multiple FIFO buffers. A master logic circuit generates a read clock stop signal (based on a control signal) and a write reset enable signal. Each FIFO's local buffer accepts write data using a write pointer/clock and provides data using a read pointer/clock, pausing when the read clock stops. Local logic generates write/read pointer reset signals based on the read clock stop signal. Write/read pointer logic updates pointers based on their clocks and suspends movement when their respective reset signals are active. When the read clock stops, all FIFO write/read pointers halt. Restarting the read clock enables write pointer movement, followed by read pointer movement, aligning the data.
9. The method of claim 8 , comprising, when the de-asserting of the read clock signal by the master logic circuit, enabling by each of the plurality of FIFO buffers movement of each read pointer with a predetermined delay from enablement of the write pointer.
The method of aligning data write and read operations of multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), involves a predetermined delay when de-asserting the read clock signal. Specifically, after the write pointer movement is enabled, the read pointer movement is enabled after a specific delay.
10. The method of claim 8 , comprising, when the asserting of the read clock stop signal by the master logic circuit, suspending operation of the read clock while operation of the write clock is free running.
The method of aligning data write and read operations of multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), involves suspending the read clock's operation when the master logic asserts the read clock stop signal. During this suspension, the write clock operates freely, allowing write operations to continue.
11. The method of claim 8 , comprising generating, with a latch of the local logic circuit, i) the write pointer reset signal as the write reset enable signal after a predetermined number of cycles of the write clock, and ii) a read pointer reset signal based on the read clock stop signal.
The method of aligning data write and read operations of multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), includes generating the write pointer reset signal using a latch in the local logic circuit as the write reset enable signal after a defined number of write clock cycles. Additionally, the read pointer reset signal is created based on the read clock stop signal.
12. The method of claim 8 , comprising generating, by a plurality of latches of the local logic circuit, the read pointer reset signal after a predetermined number of cycles of the read clock.
The method of aligning data write and read operations of multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment), involves the local logic circuit utilizing multiple latches. These latches generate the read pointer reset signal after a specified number of read clock cycles, introducing a delay.
13. The method of claim 8 , wherein the method is embodied as steps of a processor of a Serializer-Deserializer (SerDes) device.
The method of aligning data write and read operations of multiple FIFO buffers (where a master logic circuit asserts a read clock stop signal to halt write and read pointers, and restarts them for alignment) is implemented as steps executed by a processor within a Serializer-Deserializer (SerDes) device.
14. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for aligning data write and read operations of a plurality of first-in, first-out (FIFO) buffers, comprising the steps of: asserting, based on a control signal, a read clock stop signal and generating a write reset enable signal from the read clock stop signal; accepting, by a local buffer, write data in accordance with a write pointer and a write clock, and providing data based on a read pointer and a read clock, the local buffer placed in a suspended state when the master logic circuit asserts the read clock stop signal, generating, by a local logic circuit, i) a write pointer reset signal based on the read clock stop signal and the write reset enable signal, and ii) a read pointer reset signal based on the presence of the read clock stop signal and a predefined input value, generating and updating, by write pointer logic, the write pointer based on the write clock, and suspending, based on a presence of the write pointer reset signal, movement of the write pointer, and generating and updating, by read pointer logic, the read pointer based on the read clock, and suspending, based on a presence of the read pointer reset signal, movement of the write pointer; wherein, when the asserting of the read clock stop signal, each of the plurality of FIFO buffers suspends movement of each write pointer and each read pointer, and, when de-asserting the read clock signal, each of the plurality of FIFO buffers enables movement of each write pointer, then the read pointer, aligning data write and read operations of the plurality of FIFO buffers.
A non-transitory storage medium contains program code that, when executed, performs a method to align data write/read operations across multiple FIFO buffers. The method includes: generating a read clock stop signal (based on a control signal) and a write reset enable signal. Each FIFO's local buffer accepts write data using a write pointer/clock and provides data using a read pointer/clock, pausing when the read clock stops. Local logic generates write/read pointer reset signals based on the read clock stop signal. Write/read pointer logic updates pointers based on their clocks and suspends movement when reset signals are active. When the read clock stops, all FIFO write/read pointers halt. Restarting the read clock enables write pointer movement, followed by read pointer movement, aligning the data.
Unknown
September 9, 2014
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