Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A non-transitory machine-accessible storage medium including instructions that, when executed by a machine, cause the machine to perform a method comprising: determining a first execution time of a first thread of a process previously executed on a first processing unit of a multiprocessor; determining a second execution time of a second thread of the process previously executed on a second processing unit of the multiprocessor; adjusting a first power to the first processing unit and a second power to the second processing unit according to the first and second execution times of the first and second threads, wherein adjusting the first and second powers is for future execution of the same first and second threads of the process; and wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.
A computer storage medium contains instructions that, when executed, balance the load across a multi-core processor by adjusting power to each core. The instructions determine how long two parallel threads took to run on two different cores. Based on these run times, the instructions adjust the power supplied to each core for future runs of the same threads. The goal is to make the threads finish at roughly the same time in the future. The total power used by all cores is kept within a predefined power limit.
2. The non-transitory machine-accessible storage medium of claim 1 , wherein adjusting the first and second powers to the first and second processing units respectively includes: increasing the first power provided to the first processing unit at a future execution of the first thread in response to the first execution time being greater than the second execution time.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, includes specifically increasing the power to the first processing core if the first thread took longer to execute than the second thread in prior executions. This power increase is done when the first thread is run again in the future.
3. The non-transitory machine-accessible storage medium of claim 1 , wherein adjusting the first and second powers to the first and second processing units respectively includes: decreasing the second power provided to the second processing unit at a future execution of the second thread in response to the first execution time being greater than the second execution time.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, includes specifically decreasing the power to the second processing core if the first thread took longer to execute than the second thread in prior executions. This power decrease is done when the second thread is run again in the future.
4. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising: maintaining same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, also includes maintaining the current power levels for both cores if the two threads had approximately the same execution time in prior executions. This means no power adjustment is needed when both threads are already balanced.
5. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising: independently adjusting the first and second powers for each of the first and second processing units.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, adjusts the power levels of each core independently of the other cores. The power level of each core can be adjusted either up or down without needing to take the other core's power level into consideration at the same time.
6. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising: waiting for a period of time before adjusting the first and second powers.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, includes waiting a certain amount of time before adjusting the power levels to the cores. This delay could be used to allow for measurement errors or fluctuations in processor load before applying power adjustments.
7. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising: halting load balancing when a number of attempts for load balancing exceed a threshold.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, has a built-in limit. Load balancing stops if the number of attempts to adjust power exceeds a pre-defined maximum threshold. This prevents the system from endlessly trying to balance if it's not converging.
8. The non-transitory machine-accessible storage medium of claim 1 , wherein adjusting the first power to the first processing unit and the second power to the second processing unit is to effectuate the first and second threads of the process to finish executing at approximately the same time in future executions of the first and second threads of the process.
The method for load balancing described previously involves adjusting the power levels of the cores to make the threads execute in roughly the same amount of time. By tuning power to different cores, the threads should complete as close as possible in order to maximize throughput. This occurs during future execution of those same threads.
9. The non-transitory machine-accessible storage medium of claim 8 , wherein the future executions of the first and second threads being on the first and second processors of the multiprocessor respectively.
The load balancing method described previously, where power is adjusted to make threads finish at approximately the same time, specifically applies when those threads are running on their original cores in future executions. Power adjustments are linked to specific core-thread pairings.
10. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising: determining N execution times of N threads executing on N processing units of the multiprocessor, wherein the N threads are in addition to the first and second threads; and maintaining same power to the N processing units in response to the N execution times being between the first and second execution times.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, can also be extended to handle multiple threads. It determines execution times for N threads running on N cores. If the execution times of those N threads fall within the range of the execution times of the original two threads, the method holds power to the N cores at the current level.
11. The non-transitory machine-accessible storage medium of claim 10 , wherein the method is performed on a subset of the N threads.
The load balancing method for multiple threads described previously, where power is maintained when execution times are similar, does not necessarily need to apply to all threads simultaneously. The method can be applied to only a subset of available threads.
12. The non-transitory machine-accessible storage medium of claim 1 , wherein adjusting the first and second powers comprises adjusting the first and second powers by a predetermined amount.
The method for load balancing described previously, where power to cores is adjusted based on thread execution times, adjusts the power levels of each core by a fixed amount each time. This predetermined amount ensures a consistent change in power.
13. A method comprising: determining a first execution time of a first thread of a process previously executed on a first processing unit of a multiprocessor; determining a second execution time of a second thread of the process previously executed on a second processing unit of the multiprocessor; adjusting a first power to the first processing unit and a second power to the second processing unit according to the first and second execution times of the first and second threads, wherein adjusting the first and second powers is for future execution of the same first and second threads of the process; and wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.
A method balances the load across a multi-core processor by adjusting power to each core. It determines how long two parallel threads took to run on two different cores. Based on these run times, the method adjusts the power supplied to each core for future runs of the same threads. The goal is to make the threads finish at roughly the same time in the future. The total power used by all cores is kept within a predefined power limit.
14. The non-transitory machine-accessible storage medium of claim 1 , wherein the instructions are to be executed in at least one of: a user-level runtime environment or kernel layer.
The load balancing method described previously, where power to cores is adjusted based on thread execution times, can be run in either a user-level runtime environment or the operating system kernel layer.
15. A multiprocessor comprising: a first processing unit to operate at a first power; and a second processing unit to operate at a second power; wherein an asymmetric power throttling module to cause adjustment of the first power to the first processing unit and the second power to the second processing unit according to first and second execution times of previously executed first and second threads of a process, wherein the first and second threads are previously executed on the first and second processing units respectively, wherein the adjustment of the first and second powers is for future execution of the same first and second threads of the process; and wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.
A multi-core processor that balances load by adjusting the power given to each core. It contains two cores, each operating at a certain power level. An "asymmetric power throttling module" adjusts the power to each core depending on how long threads took to run previously on those cores. These power adjustments are made for future runs of the same threads. The total power used by all cores remains below a defined power limit.
16. The multiprocessor of claim 15 further comprises a power control unit which is operable to adjust the first and second powers to the corresponding first and second processing units.
The multi-core processor with load balancing described previously, including a power throttling module, contains a "power control unit" that specifically handles adjusting the power supplied to each individual core. This unit implements the core-specific power changes determined by the power throttling module.
17. The multiprocessor of claim 15 further comprises one or more logic units to determine the first and second execution times of the first and second threads of the process.
The multi-core processor with load balancing described previously, including a power throttling module, includes "logic units" that measure and record how long each thread took to execute on each core. These measured execution times are used by the power throttling module to calculate power adjustments.
18. The multiprocessor of claim 15 , wherein the asymmetric power throttling module to increase power provided to the first processing unit and to decrease power provided to the second processing unit in response to the first execution time of the first thread being substantially greater than the second execution time of a second thread.
In the multi-core processor with load balancing described previously, the power throttling module increases the power to the first core and decreases the power to the second core if the first thread took significantly longer than the second thread during previous executions.
19. The multiprocessor of claim 15 , wherein the asymmetric power throttling module to cause the first and second processing units to maintain same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.
In the multi-core processor with load balancing described previously, the power throttling module keeps the power at its current level for both cores if the two threads took approximately the same time to execute. This avoids unnecessary power adjustments when the system is already balanced.
20. The multiprocessor of claim 15 , wherein the asymmetric power throttling module is implemented at least in one of: a hardware logic or in an operating system.
The asymmetric power throttling module in the multi-core processor with load balancing described previously can be implemented in hardware logic, or in the operating system. The module can therefore reside in either the underlying hardware or the software layer.
21. The multiprocessor of claim 15 , wherein the first and second processing units are positioned in a single die.
In the multi-core processor with load balancing described previously, the multiple cores reside on the same physical chip. This single-die configuration allows for more efficient communication and power management between the cores.
22. The multiprocessor of claim 15 further comprises logic to delay adjusting of the first and second powers.
The multi-core processor with load balancing described previously includes logic to delay power adjustments. The power adjustments are therefore applied only after a certain delay.
23. The multiprocessor of claim 15 , wherein the first and second processing units implement at least one or more of: simultaneous multi-threading or symmetric processing.
In the multi-core processor with load balancing described previously, the cores can implement either simultaneous multi-threading (SMT) or symmetric multiprocessing (SMP), or one or more techniques.
24. A computer system comprising: a network communication interface; and a multiprocessor coupled to the network communication interface, the multiprocessor including: a first processing unit to operate at a first power; a second processing unit to operate at a second power; wherein an asymmetric power throttling module to cause adjustment of the first power to the first processing unit and the second power to the second processing unit according to first and second execution times of previously executed first and second threads of a process, wherein the first and second threads previously executed on the first and second processing units respectively, and wherein the adjustment of the first and second powers is for future execution of the same first and second threads of the process; and wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.
A computer system includes a network interface and a multi-core processor. The processor balances load by adjusting power to each core. It contains two cores, each operating at a certain power level. An "asymmetric power throttling module" adjusts the power to each core depending on how long threads took to run previously on those cores. These power adjustments are made for future runs of the same threads. The total power used by all cores remains below a defined power limit.
25. The computer system of claim 24 , wherein the multiprocessor further comprises a power control unit operable to adjust the first and second powers to the corresponding first and second processing units.
The computer system with multi-core load balancing described previously, which has an asymmetric power throttling module, also includes a "power control unit" which specifically controls the power supplied to each core. This unit carries out the power level changes determined by the power throttling module.
26. The computer system of claim 24 , wherein the asymmetric power throttling module to increase power provided to the first processing unit and to decrease power provided to the second processing unit in response to the first execution time of the first thread being substantially greater than the second execution time of a second thread.
In the computer system with multi-core load balancing described previously, the power throttling module increases the power to the first core and decreases the power to the second core if the first thread took significantly longer than the second thread during previous executions.
27. The computer system of claim 24 , wherein the asymmetric power throttling module to cause the first and second processing units to maintain same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.
In the computer system with multi-core load balancing described previously, the power throttling module maintains the existing power levels for both cores if the two threads took approximately the same amount of time to execute previously.
28. The computer system of claim 24 , wherein the asymmetric power throttling module is implemented at least in one of: a hardware logic or in an operating system.
The asymmetric power throttling module in the computer system with multi-core load balancing described previously can be implemented either in the hardware or in the operating system. Therefore, the module may be located in either the underlying hardware or in the software level.
29. The computer system of claim 24 , wherein the first and second processing units are positioned in a single die.
In the computer system with multi-core load balancing described previously, the multiple cores are positioned on a single physical chip. This allows for better communication and power management between the cores.
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September 16, 2014
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