Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for providing virtual data loopback in a computing system including a first instruction executing device, a second instruction executing device, and multiple interfaces for connecting the computing system with an external computing system, the method comprising: forwarding a data packet from the first instruction executing device to the second instruction executing device; the second instruction executing device identifying egress interface information from the data packet, the egress interface information indicating a first interface for forwarding the data packet out of the computing system; based on the identified egress interface information indicating the first interface, the second instruction executing device automatically determining a second interface corresponding to the first interface; the second instruction executing device inserting into the data packet ingress interface information that indicates the determined second interface; the second instruction executing device forwarding the data packet, including the ingress interface information, back to the first instruction executing device; and the first instruction executing device identifying from the data packet the ingress interface information that indicates the determined second interface; such that the data packet is looped back to the first instruction executing device without being communicated via the first or second interface, and such that from the perspective of the first instruction executing device the data packet was received via the second interface; wherein the first instruction executing device and the second instruction executing device each comprise at least one of a processor or a configurable logic device.
A computing system performs virtual data loopback. A first processing unit (processor or FPGA) sends a data packet to a second processing unit (processor or FPGA). The second unit examines the packet to find the intended output interface. Instead of sending the packet to that output, the second unit finds a corresponding *input* interface and inserts this information into the packet. The second unit sends the modified packet back to the first unit. The first unit reads the inserted input interface information, making it appear as though the packet was received on that interface, even though no actual data transmission occurred over any external interface. The packet is effectively looped back internally within the system.
2. The method of claim 1 , wherein the first instruction executing device comprises a processor and the second instruction executing device comprises a configurable logic device.
The virtual data loopback method from the previous description involves a processor sending a data packet to a configurable logic device. The configurable logic device then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the processor to simulate loopback.
3. The method of claim 2 , wherein the configurable logic device comprises a field programmable gate array (FPGA).
The virtual data loopback method, where a processor sends a data packet to a configurable logic device, specifically uses a field-programmable gate array (FPGA) as the configurable logic device for identifying the output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the processor.
4. The method of claim 1 , wherein the first instruction executing device comprises a first configurable logic device and the second instruction executing device comprises a second configurable logic device.
The virtual data loopback method uses two configurable logic devices. A first configurable logic device sends a data packet to a second configurable logic device. The second device then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the first configurable logic device to simulate loopback.
5. The method of claim 4 , wherein the first instruction executing device comprises a first FPGA and the second instruction executing device comprises a second FPGA.
The virtual data loopback method, where two configurable logic devices are used, specifically uses two FPGAs. A first FPGA sends a data packet to a second FPGA. The second FPGA then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the first FPGA.
6. The method of claim 1 , wherein the second instruction executing device determines the second interface corresponding to the first interface using a lookup table that links particular ones of the multiple interfaces to each other.
The virtual data loopback method involves the second processing unit using a lookup table to determine which input interface corresponds to the intended output interface. The lookup table contains mappings between different interfaces, allowing the system to quickly identify the correct input interface to simulate the loopback.
7. The method of claim 1 , further comprising, before forwarding the data packet back to the first instruction executing device, the second instruction executing device: determines whether to capture the data packet based on data capture instructions; and if it is determined to capture the data packet, the second instruction executing device storing a copy of the data packet in a memory device coupled to the second instruction executing device.
The virtual data loopback method includes a data capture feature. Before the second processing unit sends the data packet back to the first processing unit, it checks if data capture is enabled. If so, the second processing unit stores a copy of the data packet in a memory device connected to it, allowing for debugging or analysis. Then, the second processing unit sends the data packet with the ingress interface information back to the first processing unit.
8. A computing system, comprising: a first instruction executing device; a second instruction executing device; and multiple interfaces for connecting the computing system with an external computing system; wherein the second instruction executing device is programmed to: receive a data packet forwarded from the first instruction executing device; identify egress interface information from the data packet, the egress interface information indicating a first interface for forwarding the data packet out of the computing system; based on the identified egress interface information indicating the first interface, automatically determine a second interface corresponding to the first interface; insert into the data packet ingress interface information that indicates the determined second interface; and forward the data packet, including the ingress interface information, back to the first instruction executing device; and wherein the first instruction executing device is programmed to identify from the data packet the ingress interface information that indicates the determined second interface; such that the data packet is looped back to the first instruction executing device without being communicated via the first or second interface, and such that from the perspective of the first instruction executing device the data packet was received via the second interface; wherein the first instruction executing device and the second instruction executing device each comprise at least one of a processor or a configurable logic device.
A computing system performs virtual data loopback. It contains a first processing unit (processor or FPGA), a second processing unit (processor or FPGA), and multiple interfaces for external connections. The second unit receives a data packet from the first unit, identifies the intended output interface, finds a corresponding *input* interface, and inserts this information into the packet. It sends the modified packet back to the first unit. The first unit reads the inserted input interface information, making it appear as though the packet was received on that interface, even though no actual data transmission occurred over any external interface. The packet is effectively looped back internally within the system.
9. The system of claim 8 , wherein the first instruction executing device comprises a processor and the second instruction executing device comprises a configurable logic device.
The virtual data loopback system from the previous description uses a processor as the first processing unit and a configurable logic device as the second processing unit. The processor sends a data packet to the configurable logic device, which then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the processor to simulate loopback.
10. The system of claim 9 , wherein the configurable logic device comprises a field programmable gate array (FPGA).
The virtual data loopback system, where a processor communicates with a configurable logic device, specifically uses a field-programmable gate array (FPGA) as the configurable logic device for identifying the output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the processor.
11. The system of claim 8 , wherein the first instruction executing device comprises a first configurable logic device and the second instruction executing device comprises a second configurable logic device.
The virtual data loopback system consists of a first configurable logic device and a second configurable logic device. The first configurable logic device sends a data packet to the second configurable logic device. The second device then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the first configurable logic device to simulate loopback.
12. The system of claim 11 , wherein the first instruction executing device comprises a first FPGA and the second instruction executing device comprises a second FPGA.
The virtual data loopback system, where two configurable logic devices are used, specifically uses two FPGAs. A first FPGA sends a data packet to a second FPGA. The second FPGA then performs the steps of identifying the intended output interface, determining a corresponding input interface, inserting that information into the packet, and sending the packet back to the first FPGA.
13. The system of claim 8 , wherein the second instruction executing device is programmed to determine the second interface corresponding to the first interface using a lookup table that links particular ones of the multiple interfaces to each other.
The virtual data loopback system involves the second processing unit using a lookup table to determine which input interface corresponds to the intended output interface. The lookup table contains mappings between different interfaces, allowing the system to quickly identify the correct input interface to simulate the loopback.
14. The system of claim 8 , wherein the second instruction executing device is further programmed to, before forwarding the data packet back to the first instruction executing device: determine whether to capture the data packet based on data capture instructions; and if it is determined to capture the data packet, the second instruction executing device store a copy of the data packet in a memory device coupled to the second instruction executing device.
The virtual data loopback system includes a data capture feature. Before the second processing unit sends the data packet back to the first processing unit, it checks if data capture is enabled. If so, the second processing unit stores a copy of the data packet in a memory device connected to it, allowing for debugging or analysis. Then, the second processing unit sends the data packet with the ingress interface information back to the first processing unit.
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December 16, 2014
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