Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A shift register circuit comprising: an input terminal, first and second output terminals, and first and second clock terminals; a first transistor that supplies said first output terminal with a first clock signal inputted to said first clock terminal; a second transistor that supplies said second output terminal with a second clock signal inputted to said second clock terminal; a third transistor that charges a first node to which a control electrode of said first transistor connects, in response to activation of an input signal inputted to said input terminal; and a fourth transistor that charges a second node to which a control electrode of said second transistor connects, in response to activation of said input signal, wherein said first clock signal and said second clock signal have a same phase, and a setting is possible such that only said second clock signal is activated and the first clock signal is kept at an inactive level in a particular period.
The shift register circuit enhances the driving capability and improves the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. It comprises: an input terminal, first and second output terminals, and first and second clock terminals; a first transistor that supplies the first output terminal with a first clock signal inputted to the first clock terminal; a second transistor that supplies the second output terminal with a second clock signal inputted to the second clock terminal; a third transistor that charges a first node (connected to the control electrode of the first transistor), in response to activation of an input signal inputted to the input terminal; and a fourth transistor that charges a second node (connected to the control electrode of the second transistor), in response to activation of the input signal. The first clock signal and the second clock signal have the same phase, and a setting is possible such that only the second clock signal is activated and the first clock signal is kept at an inactive level during a specific time period (display ineffective period).
2. The shift register circuit according to claim 1 , further comprising: a fifth transistor that discharges said first output terminal; and a sixth transistor that discharges said second output terminal; wherein a control electrode of said fifth transistor and a control electrode of said sixth transistor are connected to each other.
The shift register circuit from the previous description, which includes an input terminal, first and second output terminals, and first and second clock terminals, a first transistor supplying the first output terminal with a first clock signal, a second transistor supplying the second output terminal with a second clock signal, a third transistor charging a first node in response to an input signal, and a fourth transistor charging a second node in response to the input signal, where the first and second clock signals have the same phase and only the second clock signal can be activated during a particular period, further includes: a fifth transistor that discharges the first output terminal; and a sixth transistor that discharges the second output terminal. A control electrode of the fifth transistor and a control electrode of the sixth transistor are connected to each other, allowing simultaneous discharge of the first and second output terminals.
Unknown
December 16, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.