Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and a virtual pixel clock circuit that is operative to provide a plurality of virtual pixel clock signals in response to the common clock signal, wherein a first of the plurality of virtual pixel clock signals is at a different clock speed than the common clock signal while a second of the plurality of virtual pixel clock signals is simultaneously at a different clock speed than both the first of the plurality of virtual pixel clock signals and the common clock signal, and wherein the clock speeds of the first and second of the plurality of virtual pixel clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first of the plurality of displays that operates using the first of the plurality of virtual pixel clock signals and the second of the plurality of displays that operates using the second of the plurality of virtual pixel clock signals, respectively, wherein the display configuration information from the first of the plurality of displays describes operating characteristics of the first of the plurality of displays and the display configuration information from the second of the plurality of displays describes operating characteristics of second of the plurality of displays.
A system drives multiple displays using a common clock signal. It includes a clock circuit that creates a base clock signal from a reference. A "virtual pixel clock circuit" then generates multiple pixel clock signals from this base clock. Importantly, each pixel clock runs at a different speed. The system adjusts the speed of each pixel clock based on display configuration information (type, make, characteristics) received from each connected display, simultaneously driving each display at its required clock speed.
2. The apparatus of claim 1 wherein the virtual pixel clock circuit comprises a plurality of discrete time oscillator circuits that are each operative to provide a respective one of the plurality of virtual pixel clock signals in response to the common clock signal.
The display system described previously uses a virtual pixel clock circuit that contains multiple "discrete time oscillator" circuits. Each oscillator generates one of the different pixel clock signals from the common clock signal. This allows for independent control of each pixel clock's frequency.
3. The apparatus of claim 2 further comprising a discrete time oscillator control circuit that is operative to selectively adjust a scaling factor of each of the plurality of discrete time oscillator circuits in response to the display configuration information.
The display system described previously, which utilizes discrete time oscillators, also includes a "discrete time oscillator control circuit." This control circuit adjusts a scaling factor (multiplier) of each individual oscillator. This adjustment is based on the display configuration information received from each display, allowing for precise tuning of each pixel clock's frequency.
4. The apparatus of claim 2 wherein each of the plurality of discrete time oscillator circuits is operative to selectively adjust a respective one of the virtual pixel clock signals to one of a higher and lower clock speed based on the display configuration information.
In the previously described display system using discrete time oscillators, each oscillator can selectively adjust its pixel clock signal to a higher or lower speed. This adjustment is based directly on the display configuration information from the respective display, enabling adaptive clocking based on display requirements.
5. The apparatus of claim 1 further comprising a plurality of display control circuits, each operatively responsive to a respective one of the plurality of virtual pixel clock signals.
The display system, as described previously, includes multiple display control circuits. Each of these circuits is driven by one of the virtual pixel clock signals. This allows each display controller to operate using its uniquely clocked signal.
6. The apparatus of claim 1 wherein the display configuration information includes at least one of a type and make information of the respective display.
In the previously described display system, the display configuration information includes at least the type and manufacturer of each connected display. This information is used to determine the appropriate pixel clock speed for each display.
7. The apparatus of claim 1 further comprising the plurality of displays each operative to present an image in response to a respective one of the plurality of virtual pixel clock signals.
The display system described previously also includes the displays themselves. Each display receives its respective virtual pixel clock signal and uses it to present an image. The system dynamically adjusts each display's clock signal based on the display's needs.
8. A method of driving a plurality of displays, comprising: providing a common clock signal synthesized from a reference clock signal; and providing a plurality of virtual pixel clock signals in response to the common clock signal, wherein a first of the plurality of virtual pixel clock signals is at a different clock speed than the common clock signal while a second of the plurality of virtual pixel clock signals is simultaneously at a different clock speed than both the first of the plurality of virtual pixel clock signals and the common clock signal, wherein providing the plurality of virtual pixel clock signals comprises adjusting the clock speeds of the first and second of the plurality of virtual pixel clock signals in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first of the plurality of displays that operates using the first of the plurality of virtual pixel clock signals and the second of the plurality of displays that operates using the second of the plurality of virtual pixel clock signals, respectively, wherein the display configuration information from the first of the plurality of displays describes operating characteristics of the first of the plurality of displays and the display configuration information from the second of the plurality of displays describes operating characteristics of second of the plurality of displays.
A method for driving multiple displays involves creating a common clock signal derived from a reference. The method then generates multiple "virtual pixel clock signals" from this common clock, where each pixel clock signal runs at a different speed. The speed of each pixel clock signal is adjusted based on display configuration information received from each display. The displays are then simultaneously driven using their respective pixel clock speeds.
9. The method of claim 8 comprising providing the common clock signal to a plurality of discrete time oscillator circuits that are each operative to provide a respective one of the plurality of virtual pixel clock signals in response to the common clock signal.
The display driving method described previously utilizes multiple "discrete time oscillator circuits." A common clock signal is provided to each of these circuits, and each oscillator generates one of the virtual pixel clock signals in response.
10. The method of claim 9 comprising selectively adjusting a scaling factor of each of the plurality of discrete time oscillator circuits in response to the display configuration information.
The display driving method described previously, which uses discrete time oscillators, also involves selectively adjusting a scaling factor for each oscillator circuit. This adjustment is based on the display configuration information, allowing fine-grained control over each pixel clock's frequency.
11. The method of claim 8 further comprising selectively adjusting the common clock signal to one of a higher and lower clock speed based on the display configuration information.
The display driving method can further adjust the common clock signal itself to either a higher or lower speed. This adjustment is based on the display configuration information.
12. The method of claim 8 further comprising providing each of the plurality of virtual pixel clock signals to a respective one of a plurality of video display controllers.
The display driving method further provides each virtual pixel clock signal to a respective video display controller.
13. The method of claim 8 wherein the display configuration information includes at least one of a type and make information of the respective display.
The display driving method uses display configuration information that contains at least the display's type and manufacturer. This data assists in determining the ideal pixel clock speed for the display.
14. A non-transitory computer readable medium comprising information that when executed by at least one processor causes the layout of an integrated circuit that comprises: a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and a virtual pixel clock circuit that is operative to provide a plurality of virtual pixel clock signals in response to the common clock signal, wherein a first of the plurality of virtual pixel clock signals is at a different clock speed than the common clock signal while a second of the plurality of virtual pixel clock signals is simultaneously at a different clock speed than both the first of the plurality of virtual pixel clock signals and the common clock signal, and wherein the clock speeds of the first and second of the plurality of virtual pixel clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first of the plurality of displays that operates using the first of the plurality of virtual pixel clock signals and the second of the plurality of displays that operates using the second of the plurality of virtual pixel clock signals, respectively, wherein the display configuration information from the first of the plurality of displays describes operating characteristics of the first of the plurality of displays and the display configuration information from the second of the plurality of displays describes operating characteristics of second of the plurality of displays.
A non-transitory computer-readable medium stores instructions to create an integrated circuit for driving multiple displays. The circuit includes a clock circuit that creates a base clock signal. A "virtual pixel clock circuit" generates multiple pixel clock signals from this base clock. Each pixel clock runs at a different speed. The circuit adjusts the speed of each pixel clock based on display configuration information (type, make, characteristics) received from each connected display, simultaneously driving each display at its required clock speed.
15. The non-transitory computer readable medium of claim 14 wherein the virtual pixel clock circuit comprises a plurality of discrete time oscillator circuits that are each operative to provide a respective one of the plurality of virtual pixel clock signals in response to the common clock signal.
The non-transitory computer-readable medium described previously defines an integrated circuit where the virtual pixel clock circuit contains multiple "discrete time oscillator" circuits. Each oscillator generates one of the different pixel clock signals from the common clock signal.
16. The non-transitory computer readable medium of claim 15 further comprising a discrete time oscillator control circuit that is operative to selectively adjust a scaling factor of each of the plurality of discrete time oscillator circuits in response to the display configuration information.
The non-transitory computer-readable medium, previously described, also includes instructions for a "discrete time oscillator control circuit." This control circuit adjusts a scaling factor of each individual oscillator based on the display configuration information, allowing for precise tuning of each pixel clock's frequency.
17. The non-transitory computer readable medium of claim 15 wherein each of the plurality of discrete time oscillator circuits is operative to selectively adjust the common clock signal to one of a higher and lower clock speed based on the display configuration information.
In the non-transitory computer-readable medium's description of the integrated circuit, each discrete time oscillator can selectively adjust the common clock signal to a higher or lower speed based on the display configuration information.
18. The non-transitory computer readable medium of claim 14 further comprising a plurality of display control circuits, each operatively responsive to a respective one of the plurality of virtual pixel clock signals.
A system for managing display outputs in a computing environment addresses the challenge of efficiently controlling multiple display devices with varying refresh rates and resolutions. The system includes a plurality of virtual pixel clock signals, each synchronized to a different display device, ensuring precise timing for rendering visual content. Each display control circuit is operatively responsive to a respective virtual pixel clock signal, enabling independent control of each display device. The circuits handle tasks such as frame buffering, timing adjustments, and signal formatting to match the requirements of the connected displays. This approach allows for seamless multi-display operation, reducing latency and improving synchronization across devices. The system dynamically adjusts to changes in display configurations, such as adding or removing displays, without requiring manual recalibration. By decoupling the timing control from a single master clock, the system enhances flexibility and performance in multi-display setups, particularly in applications requiring high precision, such as gaming, video editing, or professional graphics work. The solution ensures consistent visual output across all displays while minimizing resource overhead.
19. The non-transitory computer readable medium of claim 14 wherein the display configuration information includes at least one of a type and make information of the respective display.
In the non-transitory computer-readable medium's integrated circuit design, the display configuration information includes at least the type and manufacturer of each connected display.
20. The non-transitory computer readable medium of claim 14 wherein the information comprises hardware description language.
The non-transitory computer readable medium, as described previously, uses Hardware Description Language (HDL) to define the integrated circuit layout.
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September 12, 2017
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