Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A digital signal processor comprising: a DRAM including multiple memory cells configured to store data in a parasitic capacitor, and dual ports configured to perform a read operation and a write operation at the same time; and a core logic configured to perform an operation of recording, reading, or updating data in the DRAM on the basis of a predetermined digital signal processing architecture; wherein the core logic is configured to record input data in a memory cell of the DRAM and omit a refresh operation by reading the recorded input data before a retention time passes, and storing the recorded input data in another memory cell of the DRAM; and wherein the retention time is a basis of a traceback depth and a clock cycle of the predetermined digital signal processing architecture.
A digital signal processor contains DRAM memory cells which store data as charge in parasitic capacitors, and a core logic unit. The DRAM includes dual ports that can read and write simultaneously. The core logic records input data into a DRAM memory cell, then, before the charge leaks away (before the DRAM retention time expires), reads that data back and stores it in another DRAM memory cell. This bypasses the need for DRAM refresh cycles. The DRAM retention time, which is the time before data loss occurs, determines the maximum traceback depth of the digital signal processing architecture and the clock cycle time of the processor.
2. The digital signal processor of claim 1 , wherein the digital signal processing architecture is any one of a Viterbi decoder, a FFT processor, or a LDPC decoder.
The digital signal processor described as containing DRAM memory cells which store data as charge in parasitic capacitors, and a core logic unit where the DRAM includes dual ports that can read and write simultaneously, and the core logic records input data into a DRAM memory cell, then before the DRAM retention time expires, reads that data back and stores it in another DRAM memory cell, further specifies that the underlying digital signal processing algorithm can be a Viterbi decoder, a Fast Fourier Transform (FFT) processor, or a Low-Density Parity-Check (LDPC) decoder.
3. A data inputting/outputting method in a digital signal processor, comprising: recording input data in a DRAM including multiple memory cells configured to store data in a parasitic capacitor; and reading the recorded input data before a retention time of the DRAM passes, and storing the recorded input data in another memory cell of the DRAM without a refresh operation; wherein the recording and the reading are performed on the basis of a predetermined digital signal processing architecture; and wherein the retention time is a basis of a traceback depth and a clock cycle of the predetermined digital signal processing architecture.
A method for inputting and outputting data in a digital signal processor works by recording input data into a DRAM memory cell which stores data as charge in a parasitic capacitor. Before the charge leaks away (before the DRAM retention time expires), the data is read back from the memory cell and stored in a different DRAM memory cell. This is done without performing a DRAM refresh operation. This recording and reading process relies on a predetermined digital signal processing architecture. The DRAM retention time determines the maximum traceback depth of the digital signal processing architecture and the processor's clock cycle time.
4. The data inputting/outputting method of claim 3 , wherein the DRAM includes an input port and an output port.
The data input/output method where input data is recorded in a DRAM memory cell that stores data as charge in a parasitic capacitor, and before the DRAM retention time expires the data is read and stored in another memory cell, specifies that the DRAM includes separate input and output ports. This allows simultaneous read and write operations to the DRAM.
5. The data inputting/outputting method of claim 3 , wherein the digital signal processing architecture is any one of a Viterbi decoder, a FFT processor, or a LDPC decoder.
The data input/output method where input data is recorded in a DRAM memory cell that stores data as charge in a parasitic capacitor, and before the DRAM retention time expires the data is read and stored in another memory cell without refresh, based on a predetermined digital signal processing architecture, specifies that the digital signal processing architecture is any one of a Viterbi decoder, a FFT processor, or a LDPC decoder.
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October 3, 2017
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