Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for managing an operational state of a retimer circuit included in an interconnect between a host system and a device system, the method comprising: monitoring, during a first retimer operation state, a detection status of a first receiver included in the host system and coupled to a first port of the retimer circuit and a detection status of a second receiver included in a device system and coupled to a second port of the retimer circuit; responsive to the detection status of the first receiver and the detection status of the second receiver indicating the presence of the first and second receivers, transitioning from the first retimer operation state to a second retimer operation state; during the second retimer operation state: monitoring at a first specified monitoring interval the detection status of the first receiver and the detection status of the second receiver, detecting a control signal, wherein the detected control signal is associated with a ping message and a polling message, decoding the polling message responsive to detecting the control signal in the absence of an occurrence of the ping message within the first specified monitoring interval, and determining a link speed of the interconnect system based on the decoding; and enabling a data path between the host system and the device system at the determined link speed.
Interconnect circuit management. This invention addresses the need to efficiently manage the operational state of a retimer circuit within an interconnect linking a host system and a device system. The method involves monitoring the presence of receivers on both the host and device sides of the retimer. When both receivers are detected, the retimer transitions to a second operational state. In this second state, the detection status of both receivers is monitored at a specific interval. A control signal associated with ping and polling messages is detected. If a polling message is detected without a preceding ping message within the monitoring interval, the polling message is decoded. This decoding process determines the link speed of the interconnect. Finally, a data path between the host and device systems is enabled at this determined link speed.
2. The method of claim 1 , further comprising: during the second retimer operation state, monitoring at a second specified monitoring interval the detection status of the first receiver and the detection status of the second receiver; and transitioning from the second retimer operation state to the first retimer operation state when the detection status indicates that a receiver termination is not detected on the first or the second port within the second specified monitoring interval.
This method checks if devices are connected to the retimer chip's ports. If a device disconnects, the chip switches back to a lower power mode.
3. The method of claim 1 , further comprising: during the second retimer operation state, monitoring at a second specified monitoring interval the detection status of the first receiver and detection status of the second receiver; detecting the control signal; and disabling monitoring the detection status responsive to detecting the control signal.
This invention relates to a method for managing retimer operations in a communication system, particularly for monitoring receiver detection status during retimer operation states. The method addresses the challenge of efficiently monitoring receiver detection status while minimizing unnecessary power consumption and processing overhead. The method involves a system with at least two receivers and a retimer that operates in multiple states, including a first and second retimer operation state. During the second retimer operation state, the method monitors the detection status of the first and second receivers at a second specified monitoring interval. The detection status indicates whether the receivers are actively detecting signals. The method also detects a control signal, which may be generated by an external source or internal logic. Upon detecting the control signal, the method disables the monitoring of the detection status, thereby conserving system resources and power. The first retimer operation state may involve initializing or configuring the retimer, while the second retimer operation state may involve active signal retiming or error detection. The monitoring interval in the second state is distinct from any interval used in the first state, allowing for optimized performance based on the operational context. The control signal serves as a trigger to halt monitoring, which can be useful in scenarios where continuous monitoring is no longer necessary or when the system transitions to a different operational mode. This method ensures efficient resource utilization while maintaining reliable communication system performance.
4. The method of claim 1 , wherein the interconnect system is a universal serial bus (USB) interconnect system.
A method for improving data transfer efficiency in electronic devices involves using a universal serial bus (USB) interconnect system to facilitate communication between components. The USB interconnect system enables high-speed data transmission while ensuring compatibility across different devices and systems. This method addresses the need for reliable and standardized data transfer protocols in modern electronic systems, where multiple components must communicate seamlessly. The USB interconnect system may include features such as power delivery, data synchronization, and error correction to enhance performance. By integrating a USB interconnect system, the method ensures efficient data exchange while maintaining compatibility with existing and future USB standards. This approach simplifies system design and reduces the complexity of integrating multiple communication protocols, ultimately improving overall system performance and reliability. The method is particularly useful in applications requiring fast, secure, and standardized data transfer, such as computing devices, consumer electronics, and industrial systems.
5. The method of claim 4 , wherein the control signal is a low frequency periodic signal.
A system and method for controlling a device using a low-frequency periodic control signal. The invention addresses the need for precise and stable control of devices, particularly in applications where high-frequency signals may introduce noise or interference. The method involves generating a control signal characterized by a low-frequency periodic waveform, which is then applied to a device to regulate its operation. The low-frequency nature of the signal reduces susceptibility to electromagnetic interference and minimizes power consumption while maintaining accurate control. The periodic nature ensures consistent and predictable device behavior. The control signal can be adjusted in frequency, amplitude, or duty cycle to fine-tune the device's response. This approach is particularly useful in applications such as motor control, sensor calibration, and signal processing, where stability and reliability are critical. The low-frequency periodic signal may be generated using a dedicated oscillator or a programmable signal generator, and the device may include feedback mechanisms to ensure proper operation. The method ensures efficient and reliable control while mitigating the drawbacks of high-frequency signals.
6. The method of claim 1 , further comprising: determining whether a training bit is set; responsive to determining that the training bit is set, training a clock data recovery circuit included in the retimer circuit; and transitioning from the second retimer operating state to a third retimer operating state.
This invention relates to a retimer circuit used in high-speed data communication systems, specifically addressing the need for efficient clock data recovery (CDR) training and state transitions during operation. The retimer circuit operates in multiple states, including a second retimer operating state where it processes incoming data signals. The method involves determining whether a training bit is set, which indicates whether the CDR circuit requires training. If the training bit is set, the CDR circuit is trained to synchronize with the incoming data stream. After training, the retimer transitions to a third retimer operating state, which may involve normal data transmission or further adjustments. The training process ensures accurate data recovery by aligning the CDR circuit's clock with the incoming data, improving signal integrity and reducing errors. This method enhances the retimer's adaptability to varying signal conditions, ensuring reliable data transmission in high-speed communication systems. The invention focuses on optimizing the retimer's performance by dynamically adjusting its operation based on training requirements, thereby improving overall system efficiency and reliability.
7. The method of claim 6 , further comprising: detecting a loss of signal status for a threshold detecting period on the data path between the host system and the device system; and disabling the data path between the host system and the device system.
A system and method for managing data communication between a host system and a device system involves monitoring the data path for signal integrity. The method includes detecting a loss of signal status for a predefined threshold period on the data path connecting the host and device systems. Upon detecting this condition, the data path is automatically disabled to prevent further communication errors or data corruption. This approach ensures reliable data transfer by proactively addressing signal loss issues, which can occur due to physical disconnections, interference, or hardware failures. The system may include a host controller and a device controller, each responsible for managing communication protocols and error handling. The method further involves establishing a data path between the host and device systems, where the host system initiates communication by sending a request to the device system. The device system responds by transmitting data back to the host system, and the host system processes the received data. The signal monitoring mechanism continuously checks for signal integrity, and if a loss of signal is detected for the threshold period, the data path is disabled to maintain system stability. This solution is particularly useful in environments where uninterrupted and error-free data transmission is critical, such as industrial automation, medical devices, or high-speed data networks.
8. A controller circuit for determining an operational state of a retimer circuit included in an interconnect between a host system and a device system, the controller circuit including instructions that when executed by the controller circuit cause the retimer to: monitor, during a first retimer operation state, a detection status of a first receiver included in the host system and coupled to a first port of the retimer circuit and a detection status of a second receiver included in a device system and coupled to a second port of the retimer circuit; responsive to the detection status of the first receiver and the detection status of the second receiver indicating the presence of the first and second receivers, transitioning from the first retimer operation state to a second retimer operation state; during the second retimer operation state: monitor at a first specified monitoring interval the detection status of the first receiver and the detection status of the second receiver, detect a control signal, wherein the detected control signal is associated with a ping message and a polling message, decode the polling message responsive to detecting the control signal in the absence of occurrence of the ping message within the first specified monitoring interval, and determine a link speed of the interconnect system based on the decoding; and enable a data path between the host system and the device system at the determined link speed.
This invention relates to a controller circuit for managing the operational state of a retimer circuit in an interconnect system between a host system and a device system. The retimer circuit is used to improve signal integrity and extend the reach of high-speed data links. The problem addressed is ensuring reliable detection and configuration of the interconnect system, particularly in scenarios where the host and device systems may have different operational states or link speeds. The controller circuit monitors the detection status of receivers in both the host system and the device system during an initial operation state. If both receivers are detected, the retimer transitions to a second operation state. In this state, the controller periodically checks the receiver status at a specified interval. It also detects control signals, distinguishing between ping messages and polling messages. If a polling message is detected without a preceding ping message within the monitoring interval, the controller decodes the polling message to determine the link speed of the interconnect system. Once the link speed is established, the controller enables a data path between the host and device systems at the determined speed, ensuring proper communication. This approach ensures robust link initialization and speed negotiation, improving reliability in high-speed interconnect systems.
9. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to: during the second retimer operation state, monitor at a second specified monitoring interval the detection status of the first receiver and the detection status of the second receiver; and transition from the second retimer operation state to the first retimer operation state when the detection status indicates that a receiver termination is not detected on the first or the second port within the second specified monitoring interval.
This invention relates to a controller circuit for managing retimer operations in a communication system, particularly for monitoring and transitioning between operational states based on receiver detection status. The system addresses the challenge of efficiently managing power and performance in high-speed data transmission by dynamically adjusting retimer behavior in response to receiver presence or absence. The controller circuit includes a retimer circuit configured to operate in at least two states: a first retimer operation state and a second retimer operation state. In the first state, the retimer circuit performs normal data retiming functions, such as signal regeneration and error correction, to maintain reliable data transmission between connected devices. In the second state, the retimer circuit enters a reduced functionality mode, conserving power by limiting or suspending certain operations while still monitoring receiver status. During the second retimer operation state, the controller circuit monitors the detection status of two receivers—one connected to a first port and another connected to a second port—at a specified interval. If the detection status indicates that a receiver termination is not detected on either port within this interval, the controller transitions the retimer circuit back to the first operation state. This ensures that the retimer resumes full functionality when a receiver is reconnected, maintaining data integrity while optimizing power consumption when no receiver is present. The system thus balances performance and efficiency in dynamic communication environments.
10. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to: during the second retimer operation state, monitor at a second specified monitoring interval the detection status of the first receiver and detection status of the second receiver; detect the control signal; and disable monitoring the detection status responsive to detecting the control signal.
A controller circuit for managing retimer operations in high-speed data communication systems addresses the challenge of efficiently monitoring receiver detection status while minimizing unnecessary power consumption. The circuit includes a retimer circuit that operates in multiple states, including a second retimer operation state where it monitors the detection status of two receivers at a second specified monitoring interval. During this state, the retimer circuit detects a control signal and, in response, disables further monitoring of the receiver detection status. This selective monitoring reduces power usage by avoiding continuous status checks when not needed. The retimer circuit may also transition between states based on the detection status of the receivers, ensuring optimal performance and energy efficiency. The control signal can be generated by an external source or derived from internal logic, providing flexibility in managing monitoring operations. This approach enhances system reliability and power efficiency in data communication networks by dynamically adjusting monitoring activities based on operational conditions.
11. The controller circuit of claim 10 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to: resume monitoring of the detection status when the control signal is not detected during the monitoring interval.
A controller circuit for managing data transmission in high-speed communication systems, particularly addressing signal integrity issues in retimer circuits. The invention focuses on improving reliability by dynamically adjusting monitoring of signal detection status. The controller circuit includes a retimer circuit that monitors a control signal to detect its presence or absence during a defined monitoring interval. If the control signal is not detected within this interval, the retimer circuit resumes monitoring the detection status, ensuring continuous and adaptive signal assessment. This mechanism prevents false positives or negatives in signal detection, enhancing data transmission accuracy and system robustness. The controller circuit may also include additional features such as generating a reset signal to reset the retimer circuit when the control signal is detected, ensuring proper initialization and synchronization. The invention is particularly useful in applications requiring high-speed data transfer with minimal latency and high reliability, such as data centers, telecommunications, and high-performance computing environments. The adaptive monitoring approach reduces the risk of signal loss or corruption, improving overall system performance and stability.
12. The controller circuit of claim 8 , wherein the interconnect system is a universal serial bus (USB) interconnect system.
A controller circuit is designed to manage data transfer in electronic systems, particularly addressing challenges related to compatibility and efficiency in interconnect systems. The circuit includes a universal serial bus (USB) interconnect system, which facilitates high-speed data communication between devices. The USB interconnect system supports standardized protocols, ensuring seamless integration with various peripheral devices. The controller circuit also includes a data processing module that handles data formatting, error detection, and correction to maintain data integrity during transmission. Additionally, the circuit may incorporate power management features to regulate power delivery through the USB interface, optimizing energy efficiency. The system is designed to support multiple data transfer modes, including bulk, interrupt, and isochronous transfers, catering to different application requirements. The USB interconnect system may also include features for hot-swapping, allowing devices to be connected or disconnected without system interruption. The overall design aims to enhance performance, reliability, and compatibility in electronic devices that rely on USB-based communication.
13. The controller circuit of claim 8 , wherein the control signal is a low frequency periodic signal.
14. The controller circuit of claim 12 , wherein the polling message is Polling.LFPS.
A controller circuit is designed for managing communication in a networked system, particularly addressing the challenge of efficiently polling devices to maintain synchronization and data integrity. The circuit includes a polling module that generates and transmits polling messages to connected devices, ensuring timely updates and error detection. The polling message is specifically configured as Polling.LFPS, a low-frequency polling signal optimized for energy efficiency and reduced latency in communication protocols. This type of polling message is used to periodically check the status of devices, verify data transmission integrity, and synchronize operations across the network. The controller circuit also includes a response processing module that interprets incoming responses from polled devices, analyzing the data for errors or discrepancies. If an error is detected, the circuit initiates corrective actions, such as retransmission or device resynchronization. The system is particularly useful in environments where reliable and low-latency communication is critical, such as industrial automation, IoT networks, or real-time data processing systems. The use of Polling.LFPS ensures that the polling process does not overly burden the network, balancing performance with power consumption. The controller circuit may also include additional features, such as adaptive polling intervals based on network conditions or device status, further enhancing its efficiency and reliability.
15. The controller circuit of claim 12 , wherein the ping message is Ping.LFPS.
A controller circuit is designed to manage communication in a networked system, particularly addressing challenges related to link failure propagation suppression (LFPS) in high-speed data transmission. The circuit includes a processor and memory storing instructions for generating and processing ping messages to monitor and maintain link integrity. The invention focuses on a specific ping message type, Ping.LFPS, which is used to detect and mitigate link failures in a network. This message type is part of a broader system that includes generating and transmitting ping messages, receiving responses, and analyzing the responses to determine link status. The controller circuit also handles error conditions, such as timeouts or invalid responses, to ensure reliable communication. The Ping.LFPS message is designed to suppress false link failure indications, improving network stability and reducing unnecessary disruptions. The circuit may also include additional features, such as adjusting transmission parameters based on link conditions or logging diagnostic data for troubleshooting. The overall system ensures robust and efficient data transmission in environments where link failures could otherwise degrade performance.
16. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to: determine whether a training bit is set; responsive to determining that the training bit is set, train a clock data recovery circuit included in the retimer circuit; and transition from the second retimer operating state to a third retimer operating state.
This invention relates to a controller circuit for managing a retimer circuit in high-speed data communication systems, particularly addressing the need for efficient training and state transitions in retimer operations. The retimer circuit includes a clock data recovery (CDR) circuit that requires periodic training to maintain synchronization and data integrity. The controller circuit monitors a training bit to determine when training is necessary. When the training bit is set, the controller initiates training of the CDR circuit to adjust its parameters for optimal performance. After training is complete, the retimer transitions from a second operating state to a third operating state, ensuring seamless data transmission. The controller circuit also manages other retimer functions, such as receiving and processing data signals, adjusting signal integrity, and maintaining synchronization between transmitter and receiver circuits. This invention improves reliability and efficiency in high-speed data links by automating training and state transitions, reducing manual intervention and potential errors. The system is particularly useful in applications requiring low-latency, high-bandwidth communication, such as data centers, networking equipment, and high-performance computing.
17. The controller circuit of claim 16 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to: detect a loss of signal status for a threshold detecting period on the data path between the host system and the device system; and disable the data path between the host system and the device system transitioning to a third retimer operating state.
A controller circuit for managing data communication between a host system and a device system includes a retimer circuit that enhances signal integrity and reliability. The retimer circuit monitors the data path for signal degradation or loss. When a loss of signal is detected for a predefined threshold period, the controller circuit disables the data path and transitions the retimer to a third operating state. This state may involve power-saving measures, error recovery procedures, or other corrective actions to maintain system stability. The retimer circuit may also include signal conditioning features such as equalization, amplification, or clock data recovery to compensate for signal attenuation over long distances or high-speed data links. The controller circuit ensures seamless communication by dynamically adjusting retimer operations based on real-time signal conditions, preventing data corruption or transmission failures. This approach is particularly useful in high-speed interconnects, such as PCIe, USB, or Ethernet, where signal integrity is critical for reliable data transfer. The system may also include error detection and reporting mechanisms to alert the host or device of any communication issues, enabling proactive troubleshooting. The retimer circuit's ability to transition between different operating states based on signal conditions improves overall system robustness and efficiency.
Unknown
January 2, 2018
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