A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
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1. A coplanar capacitor, comprising: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer, wherein each of the plurality of bias lines has vertical sides, and wherein the plurality of bias lines are covered by an inter-level dielectric; a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent a respective vertical side of one of the plurality of bias lines, wherein each of the plurality of sidewall spacers covers a respective portion of a top of the voltage-tunable dielectric layer, wherein each of the plurality of sidewall spacers spans a respective distance between the top of the voltage-tunable dielectric layer and a top of the inter-level dielectric, and wherein each respective distance includes a full height of the respective vertical side; and metallization over the inter-level dielectric, the plurality of sidewall spacers and exposed portions of the voltage-tunable dielectric layer, wherein the metallization forms RF electrodes.
A coplanar capacitor is disclosed for use in tunable RF applications, addressing the need for compact, high-performance capacitors with adjustable capacitance. The capacitor includes a substrate supporting a voltage-tunable dielectric layer, which allows capacitance tuning via an applied bias voltage. Over this layer, multiple bias lines are arranged, each with vertical sidewalls, and are encapsulated by an inter-level dielectric. Sidewall spacers are positioned adjacent to the vertical sides of each bias line, partially covering the tunable dielectric layer and extending vertically from the dielectric layer's top surface to the top of the inter-level dielectric, fully spanning the height of the bias line sidewalls. These spacers ensure precise electrical isolation and structural support. Metallization is deposited over the inter-level dielectric, sidewall spacers, and exposed areas of the tunable dielectric layer, forming RF electrodes. The metallization creates a coplanar electrode structure, enabling efficient RF signal transmission while maintaining tunability through the underlying dielectric layer. The design optimizes capacitance density, tuning range, and RF performance in integrated circuits.
2. The coplanar capacitor of claim 1 , wherein the plurality of bias lines are encapsulated on top surfaces thereof by the inter-level dielectric, wherein the plurality of bias lines are encapsulated on side surfaces thereof by the plurality of sidewall spacers, wherein the plurality of bias lines are encapsulated on bottom surfaces thereof by the voltage-tunable dielectric layer, wherein the metallization further forms one or more interconnects between a resistive layer and one or more of the plurality of bias lines, and wherein the metallization further forms one or more of a DC bias pad, an input pad and an output pad.
This invention relates to a coplanar capacitor structure with improved encapsulation and interconnect features. The capacitor includes a voltage-tunable dielectric layer, a plurality of bias lines, and an inter-level dielectric that encapsulates the top surfaces of the bias lines. Sidewall spacers encapsulate the side surfaces of the bias lines, while the bottom surfaces remain in contact with the voltage-tunable dielectric layer. The structure further includes metallization that forms interconnects between a resistive layer and one or more of the bias lines. Additionally, the metallization forms various pads, including a DC bias pad, an input pad, and an output pad, facilitating electrical connections to the capacitor. The encapsulation and interconnect design enhances reliability and performance by protecting the bias lines from environmental and electrical interference while ensuring efficient signal routing. This configuration is particularly useful in tunable capacitor applications where precise control of dielectric properties is required, such as in RF and microwave circuits. The invention addresses challenges in maintaining stable electrical performance while integrating multiple functional elements within a compact footprint.
3. The coplanar capacitor of claim 1 , wherein the substrate comprises a silicon dioxide layer, and wherein the voltage-tunable dielectric layer is over the silicon dioxide layer.
This invention relates to a coplanar capacitor structure designed for tunable dielectric applications. The capacitor includes a substrate with a silicon dioxide layer, over which a voltage-tunable dielectric layer is deposited. The tunable dielectric layer enables dynamic adjustment of the capacitor's capacitance by applying an external voltage, allowing for applications in tunable circuits, filters, and phase shifters. The silicon dioxide layer provides electrical insulation and structural support, while the tunable dielectric layer exhibits a variable permittivity in response to an applied electric field. This configuration ensures stable performance while enabling precise capacitance control. The capacitor may also include conductive electrodes positioned adjacent to the tunable dielectric layer to form the capacitor plates. The combination of the silicon dioxide layer and the tunable dielectric layer allows for efficient voltage tuning without compromising device reliability. This design is particularly useful in radio frequency (RF) and microwave applications where adjustable capacitance is required for signal modulation and impedance matching. The invention addresses the need for compact, high-performance tunable capacitors in modern electronic systems.
4. The coplanar capacitor of claim 1 , wherein the substrate comprises ceramic, alumina ceramic, magnesium oxide, silicon, silicon dioxide, glass, sapphire, or a combination thereof.
This invention relates to a coplanar capacitor structure designed for high-frequency applications, addressing challenges in miniaturization, signal integrity, and thermal stability. The capacitor features a substrate made from materials such as ceramic, alumina ceramic, magnesium oxide, silicon, silicon dioxide, glass, sapphire, or a combination thereof, selected for their dielectric properties, thermal conductivity, and compatibility with high-frequency circuits. The substrate supports conductive electrodes arranged in a coplanar configuration, where the electrodes are positioned on the same plane, reducing parasitic effects and improving signal transmission. The materials used for the substrate ensure mechanical stability, low loss tangents, and resistance to thermal expansion, making the capacitor suitable for demanding environments. The design optimizes capacitance density while maintaining low insertion loss and high reliability, addressing limitations in traditional capacitors where substrate choice can degrade performance at high frequencies. The invention is particularly useful in RF and microwave circuits, where precise impedance matching and minimal signal distortion are critical. The substrate materials also enhance manufacturability, allowing for precise patterning and integration with other circuit components. This approach provides a robust solution for applications requiring compact, high-performance capacitors in telecommunications, aerospace, and high-speed digital systems.
5. The coplanar capacitor of claim 1 , wherein the voltage-tunable dielectric layer comprises Barium Strontium Titanate (BST), Barium Lanthanum Tantalate (BLT), Lead Titanate (PT), Lead Lanthanum Zirconate Titanate (PLZT), Strontium Bismuth Niobate (SBN), including doped compositions or multi-layer structures thereof.
This invention relates to a coplanar capacitor with a voltage-tunable dielectric layer, addressing the need for tunable capacitance in electronic circuits. The capacitor includes a first electrode and a second electrode positioned on a substrate, with a voltage-tunable dielectric layer sandwiched between them. The dielectric layer exhibits tunable dielectric properties, allowing its permittivity to be adjusted by applying an external voltage, which in turn modifies the capacitor's capacitance. The voltage-tunable dielectric layer is composed of materials such as Barium Strontium Titanate (BST), Barium Lanthanum Tantalate (BLT), Lead Titanate (PT), Lead Lanthanum Zirconate Titanate (PLZT), Strontium Bismuth Niobate (SBN), or doped compositions and multi-layer structures thereof. These materials are selected for their ability to exhibit significant changes in dielectric constant under an applied electric field, making them suitable for applications requiring tunable capacitance, such as phase shifters, tunable filters, and voltage-controlled oscillators. The capacitor's design ensures efficient voltage tuning while maintaining structural integrity and performance stability. The use of these specific dielectric materials enhances the capacitor's tunability, linearity, and reliability in high-frequency and high-power applications.
6. The coplanar capacitor of claim 1 , wherein the plurality of bias lines comprise platinum, iridium, ruthenium, osmium including their alloys and multilayer structures.
This invention relates to coplanar capacitors, which are used in integrated circuits for storing and managing electrical charge. A key challenge in designing such capacitors is ensuring reliable electrical performance while maintaining compatibility with semiconductor fabrication processes. The invention addresses this by incorporating bias lines made from high-conductivity, corrosion-resistant materials such as platinum, iridium, ruthenium, osmium, their alloys, or multilayer structures. These materials enhance electrical conductivity and durability, reducing signal loss and improving long-term stability. The bias lines are integrated into the capacitor structure to provide controlled electrical connections, ensuring efficient charge distribution and minimizing parasitic effects. The use of these specialized materials also improves resistance to oxidation and electromigration, which are common issues in semiconductor devices. This design is particularly useful in high-performance applications where reliability and efficiency are critical, such as in memory devices, RF circuits, and power management systems. The invention ensures that the capacitor operates effectively under varying environmental and operational conditions, extending its lifespan and maintaining consistent performance.
7. The coplanar capacitor of claim 1 , wherein the inter-level dielectric comprises oxide.
A coplanar capacitor structure is disclosed, addressing the need for improved capacitance density and reliability in integrated circuits. The capacitor includes a first conductive plate and a second conductive plate positioned on the same plane, separated by an inter-level dielectric layer. The inter-level dielectric layer is composed of an oxide material, which provides electrical insulation between the conductive plates while maintaining structural integrity. The oxide dielectric ensures high dielectric strength and low leakage current, enhancing the capacitor's performance. The coplanar arrangement allows for efficient integration into semiconductor devices, particularly in applications requiring compact and high-performance capacitors, such as memory cells, RF circuits, and power management systems. The oxide dielectric layer further improves thermal stability and compatibility with standard semiconductor fabrication processes, ensuring reliable operation under varying environmental conditions. This design optimizes capacitance per unit area while minimizing parasitic effects, making it suitable for advanced microelectronic applications.
8. The coplanar capacitor of claim 7 , wherein the oxide comprises dioxide low-k non-tunable dielectric.
A coplanar capacitor structure is disclosed, addressing the need for improved dielectric materials in integrated circuits to enhance performance and reduce power consumption. The capacitor includes a first conductive plate and a second conductive plate positioned on a substrate, with a dielectric layer separating the plates. The dielectric layer is composed of a low-k (low dielectric constant) non-tunable oxide material, specifically dioxide, which minimizes parasitic capacitance and signal interference while maintaining stability. The low-k dielectric reduces the overall capacitance of the structure, improving signal integrity and energy efficiency in high-frequency applications. The non-tunable nature of the dielectric ensures consistent performance across varying operating conditions. The coplanar arrangement of the conductive plates allows for compact integration within semiconductor devices, making it suitable for advanced microelectronics and radio frequency (RF) circuits. The use of dioxide as the dielectric material further enhances thermal stability and reliability, addressing challenges associated with thermal expansion and degradation in high-performance environments. This design optimizes the trade-off between capacitance, leakage current, and dielectric breakdown strength, making it particularly useful in applications requiring precise signal control and low power dissipation.
9. The coplanar capacitor of claim 1 , wherein each of the plurality of sidewall spacers comprises silicon dioxide.
A coplanar capacitor structure is disclosed that addresses challenges in semiconductor fabrication, particularly in achieving high capacitance density while maintaining reliability and manufacturability. The capacitor includes a first conductive plate and a second conductive plate positioned on a substrate, with a dielectric layer separating the plates. A key feature is the inclusion of sidewall spacers adjacent to the conductive plates, which improve structural integrity and reduce leakage currents. These spacers are composed of silicon dioxide, a material chosen for its insulating properties and compatibility with standard semiconductor processes. The silicon dioxide spacers help define the lateral boundaries of the capacitor plates, ensuring precise alignment and minimizing parasitic capacitance. This design enhances the capacitor's performance by increasing capacitance density while maintaining low leakage and high reliability. The use of silicon dioxide also simplifies integration into existing fabrication workflows, as it is widely used in semiconductor manufacturing. The overall structure is optimized for applications requiring compact, high-performance capacitors, such as memory devices and integrated circuits.
10. The coplanar capacitor of claim 1 , wherein the metallization comprises a platinum layer and one or more other conductive metal and barrier layers that are formed on the platinum layer.
This invention relates to a coplanar capacitor structure designed for improved electrical performance and reliability in integrated circuits. The capacitor is formed on a substrate and includes a first conductive plate and a second conductive plate positioned coplanar to each other, separated by a dielectric material. The metallization of the capacitor comprises a platinum layer, which serves as a conductive electrode, along with one or more additional conductive metal and barrier layers deposited on top of the platinum layer. The additional layers may include materials such as titanium, titanium nitride, or other conductive and barrier metals to enhance adhesion, reduce diffusion, and improve electrical conductivity. The platinum layer provides excellent corrosion resistance and high work function, while the additional layers ensure mechanical stability and compatibility with surrounding materials. This configuration is particularly useful in semiconductor devices where high capacitance density, low leakage, and long-term reliability are critical, such as in memory cells, RF circuits, or analog integrated circuits. The structure addresses challenges in conventional capacitors, such as electrode degradation and interface instability, by using a robust metallization scheme that maintains performance under harsh operating conditions.
11. A coplanar capacitor, comprising: a first dielectric layer, wherein the first dielectric layer is disposed on a substrate, wherein the substrate includes a silicon dioxide layer upon which the first dielectric layer is disposed, and wherein the first dielectric layer comprises a voltage-tunable dielectric; a plurality of bias lines, wherein the plurality of bias lines are disposed on the first dielectric layer, wherein each of the plurality of bias lines has vertical sides and wherein the plurality of bias lines comprise metal; an inter-level dielectric, wherein the inter-level dielectric is disposed on the plurality of bias lines; a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent a respective vertical side of one of the plurality of bias lines, wherein each of the plurality of sidewall spacers covers a respective portion of a top of the voltage-tunable dielectric, wherein each of the plurality of sidewall spacers spans a respective distance between the top of the voltage-tunable dielectric and a top of the inter-level dielectric, and wherein each respective distance includes a full height of the respective vertical side; and metallization over the inter-level dielectric, the plurality of sidewall spacers and exposed portions of the voltage-tunable dielectric, wherein the metallization forms RF electrodes.
This invention relates to a coplanar capacitor with a voltage-tunable dielectric layer, designed for applications requiring adjustable capacitance. The capacitor addresses the need for tunable capacitance in radio frequency (RF) circuits, where traditional fixed capacitors lack flexibility. The structure includes a substrate with a silicon dioxide layer, upon which a first dielectric layer of voltage-tunable material is deposited. This layer enables capacitance tuning by applying an external bias voltage. A plurality of metal bias lines are disposed on the first dielectric layer, each with vertical sides. An inter-level dielectric layer is formed over the bias lines, and sidewall spacers are positioned adjacent to the vertical sides of the bias lines. These spacers cover portions of the voltage-tunable dielectric and extend from its top surface to the top of the inter-level dielectric, fully spanning the height of the bias line sides. Metallization is then applied over the inter-level dielectric, sidewall spacers, and exposed areas of the voltage-tunable dielectric, forming RF electrodes. The sidewall spacers ensure proper insulation and structural integrity while allowing the tunable dielectric to function effectively. This design enables precise control of capacitance in RF applications through voltage tuning, improving performance in tunable circuits.
12. The coplanar capacitor of claim 11 , wherein the metallization further forms one or more interconnects between a resistive layer and one or more of the plurality of bias lines, and wherein the metallization further forms one or more of a DC bias pad, an input pad and an output pad.
This invention relates to a coplanar capacitor structure designed for integrated circuits, particularly addressing challenges in signal transmission and bias management in high-frequency applications. The capacitor includes a substrate with a resistive layer and a plurality of bias lines positioned on the same plane. The metallization layer forms the capacitor's electrodes and also creates interconnects that link the resistive layer to the bias lines. Additionally, the metallization layer includes conductive pads for DC bias, input, and output connections. The structure ensures efficient signal coupling while maintaining electrical isolation between different components. The resistive layer helps control signal propagation and impedance matching, while the bias lines provide stable voltage distribution. The integrated pads simplify external connections, reducing parasitic effects and improving overall performance in high-frequency circuits. This design is particularly useful in RF and microwave applications where compact, high-performance capacitors are required. The metallization layer's dual role in forming both the capacitor and interconnects optimizes space utilization and manufacturing efficiency. The invention enhances signal integrity and operational stability in advanced electronic systems.
13. The coplanar capacitor of claim 12 , wherein the metallization is deposited over the inter-level dielectric by being deposited on an oxide layer that is on the inter-level dielectric.
This invention relates to the field of semiconductor manufacturing, specifically to the design of coplanar capacitors used in integrated circuits. The problem addressed is the need for improved capacitor structures that maintain high performance while being compatible with advanced semiconductor fabrication processes. The coplanar capacitor includes a first conductive plate and a second conductive plate positioned on the same level within an integrated circuit. These plates are separated by an inter-level dielectric material, which provides electrical insulation between them. The capacitor further includes a metallization layer that is deposited over the inter-level dielectric. This metallization layer is deposited on an oxide layer that is itself deposited on the inter-level dielectric, forming a stacked structure that enhances electrical properties and reliability. The oxide layer serves as an additional insulating barrier, improving dielectric strength and reducing leakage current between the metallization and the underlying conductive plates. This design allows for precise control of the capacitor's electrical characteristics while maintaining compatibility with standard semiconductor manufacturing processes. The resulting capacitor structure is particularly useful in high-density integrated circuits where space efficiency and electrical performance are critical.
14. A coplanar capacitor, comprising: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer, wherein each of the plurality of bias lines has vertical sides, and wherein the plurality of bias lines are covered by an inter-level dielectric; a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent a respective vertical side of one of the plurality of bias lines, wherein each of the plurality of sidewall spacers covers a respective portion of a top of the voltage-tunable dielectric layer, wherein each of the plurality of sidewall spacers spans a respective distance between the top of the voltage-tunable dielectric layer and a top of the inter-level dielectric, and wherein each respective distance includes a full height of the respective vertical side; and metallization over the inter-level dielectric, the plurality of sidewall spacers and exposed portions of the voltage-tunable dielectric layer, wherein the metallization forms RF electrodes; wherein the plurality of bias lines are encapsulated on top surfaces thereof by the inter-level dielectric, wherein the plurality of bias lines are encapsulated on side surfaces thereof by the plurality of sidewall spacers, wherein the plurality of bias lines are encapsulated on bottom surfaces thereof by the voltage-tunable dielectric layer, wherein the metallization further forms one or more interconnects between a resistive layer and one or more of the plurality of bias lines, and wherein the metallization further forms one or more of a DC bias pad, an input pad and an output pad; and wherein the substrate comprises a silicon dioxide layer, and wherein the voltage-tunable dielectric layer is over the silicon dioxide layer.
A coplanar capacitor structure is designed to provide tunable capacitance in radio frequency (RF) applications. The device addresses the need for compact, high-performance capacitors with adjustable dielectric properties to enhance signal modulation and filtering. The capacitor includes a substrate with a silicon dioxide layer, over which a voltage-tunable dielectric layer is deposited. A plurality of bias lines are positioned on the dielectric layer, each with vertical sidewalls, and are fully encapsulated by an inter-level dielectric material. Sidewall spacers are formed adjacent to the vertical sides of the bias lines, covering portions of the dielectric layer and extending from the dielectric layer's top surface to the top of the inter-level dielectric. These spacers ensure electrical isolation and structural stability. Metallization is applied over the inter-level dielectric, sidewall spacers, and exposed areas of the dielectric layer, forming RF electrodes. The metallization also creates interconnects between a resistive layer and the bias lines, as well as DC bias, input, and output pads. The encapsulated bias lines are isolated on all surfaces—top, sides, and bottom—by the inter-level dielectric, sidewall spacers, and dielectric layer, respectively. This design enables precise control of the dielectric properties via applied bias voltages, improving RF performance while maintaining compactness and reliability.
15. The coplanar capacitor of claim 14 , wherein the voltage-tunable dielectric layer comprises Barium Strontium Titanate (BST), Barium Lanthanum Tantalate (BLT), Lead Titanate (PT), Lead Lanthanum Zirconate Titanate (PLZT), Strontium Bismuth Niobate (SBN), including doped compositions or multi-layer structures thereof.
This invention relates to coplanar capacitors with voltage-tunable dielectric layers, addressing the need for tunable capacitance in high-frequency and microwave applications. The capacitor structure includes a voltage-tunable dielectric layer positioned between two conductive electrodes, where the dielectric layer's permittivity can be adjusted by applying an external voltage. This tunability allows dynamic control of capacitance, which is critical for applications such as phase shifters, tunable filters, and voltage-controlled oscillators in wireless communication systems. The voltage-tunable dielectric layer is composed of materials exhibiting ferroelectric or paraelectric properties, such as Barium Strontium Titanate (BST), Barium Lanthanum Tantalate (BLT), Lead Titanate (PT), Lead Lanthanum Zirconate Titanate (PLZT), Strontium Bismuth Niobate (SBN), or variations thereof, including doped compositions or multi-layer structures. These materials enable significant changes in dielectric constant under an applied electric field, enhancing the capacitor's tunability. The electrodes are typically conductive layers, such as metals or conductive oxides, deposited on a substrate to form a coplanar structure. The invention may also include additional layers, such as buffer or adhesion layers, to improve performance and reliability. The tunable dielectric layer's composition and structure are optimized to achieve high tunability, low loss, and stability across a wide frequency range, making the capacitor suitable for high-performance RF and microwave applications.
16. The coplanar capacitor of claim 14 , wherein the plurality of bias lines comprise platinum, iridium, ruthenium, osmium including their alloys and multilayer structures.
This invention relates to coplanar capacitors, specifically addressing the need for improved bias lines in such capacitors. Coplanar capacitors are used in integrated circuits to provide capacitance between conductive layers on the same plane. A key challenge is ensuring reliable electrical performance and durability of the bias lines, which connect to the capacitor plates. The invention improves upon prior designs by specifying the use of platinum, iridium, ruthenium, osmium, or their alloys and multilayer structures for the bias lines. These materials are chosen for their high conductivity, resistance to oxidation, and stability under high-temperature and high-voltage conditions, which are common in semiconductor manufacturing and operation. The bias lines are electrically connected to the capacitor plates, which are formed on a substrate and separated by a dielectric layer. The use of these noble metals and their alloys ensures long-term reliability and minimizes signal degradation, making the capacitor suitable for high-performance applications such as RF circuits, memory devices, and power management systems. The invention focuses on enhancing the electrical and mechanical properties of the bias lines to improve overall capacitor performance.
17. The coplanar capacitor of claim 14 , wherein the inter-level dielectric comprises oxide.
A coplanar capacitor structure is disclosed, addressing the need for improved capacitance density and reliability in integrated circuits. The capacitor includes a first conductive plate and a second conductive plate positioned on the same level (coplanar) within a semiconductor device. The plates are separated by an inter-level dielectric material, which in this embodiment comprises oxide. The oxide dielectric provides electrical insulation while maintaining a compact footprint, enhancing capacitance per unit area. The coplanar arrangement simplifies fabrication compared to stacked capacitors, reducing process complexity and cost. The oxide dielectric ensures stable electrical properties, minimizing leakage and improving long-term reliability. This design is particularly useful in high-density memory and logic circuits where space efficiency and performance are critical. The use of oxide as the dielectric material balances electrical performance with manufacturability, making it suitable for advanced semiconductor applications.
18. The coplanar capacitor of claim 17 , wherein the oxide comprises dioxide low-k non-tunable dielectric.
A coplanar capacitor structure is disclosed, addressing the need for improved dielectric materials in integrated circuits to enhance performance and reduce power consumption. The capacitor features a low-k dielectric material, specifically a non-tunable dioxide, to minimize parasitic capacitance and signal delay while maintaining stability. The dielectric layer is integrated between conductive plates, ensuring a compact, planar design that is compatible with advanced semiconductor manufacturing processes. The use of a low-k dioxide dielectric reduces dielectric constant, improving signal integrity and energy efficiency in high-density circuits. This design is particularly useful in applications requiring precise capacitance control, such as RF circuits, memory devices, and high-speed digital systems. The non-tunable nature of the dielectric ensures consistent performance across varying operating conditions, eliminating the need for external tuning mechanisms. The capacitor structure is optimized for integration into existing fabrication workflows, reducing complexity and cost while enhancing overall device reliability. The invention provides a scalable solution for next-generation semiconductor technologies, addressing challenges in miniaturization and power efficiency.
19. The coplanar capacitor of claim 14 , wherein each of the plurality of sidewall spacers comprises silicon dioxide.
A coplanar capacitor structure is disclosed that addresses challenges in semiconductor fabrication, particularly in achieving high capacitance density while maintaining reliability and manufacturability. The capacitor includes a first conductive plate and a second conductive plate positioned on the same plane, with a dielectric material separating them. The structure further incorporates sidewall spacers adjacent to the conductive plates to enhance electrical insulation and structural integrity. These sidewall spacers are composed of silicon dioxide, a material known for its excellent insulating properties and compatibility with semiconductor processing. The use of silicon dioxide ensures reliable dielectric performance, reduces leakage currents, and improves the overall stability of the capacitor. The coplanar design allows for efficient integration into advanced semiconductor devices, such as memory cells or logic circuits, where compact and high-performance capacitive elements are required. The sidewall spacers also help in defining precise geometries, ensuring consistent capacitance values across the device. This configuration is particularly useful in applications where miniaturization and high-density integration are critical, such as in modern integrated circuits and microelectronic systems. The silicon dioxide spacers contribute to the robustness of the capacitor by preventing short circuits and maintaining electrical isolation between conductive elements.
20. The coplanar capacitor of claim 14 , wherein the metallization comprises a platinum layer and one or more other conductive metal and barrier layers that are formed on the platinum layer.
This invention relates to coplanar capacitors, which are used in integrated circuits to store electrical charge. A common challenge in designing such capacitors is ensuring reliable electrical performance while maintaining compatibility with semiconductor fabrication processes. The invention addresses this by providing a coplanar capacitor with a specific metallization structure that enhances conductivity and durability. The capacitor includes a conductive layer, such as platinum, which serves as a primary conductive material. Additional conductive and barrier layers are deposited on top of the platinum layer to improve adhesion, prevent diffusion, and enhance electrical properties. The barrier layers may include materials like titanium, titanium nitride, or tantalum nitride, which prevent interdiffusion between the platinum and other materials in the capacitor or surrounding circuitry. The conductive layers may include metals like aluminum or copper to improve overall conductivity. This metallization structure ensures that the capacitor maintains high electrical performance while resisting degradation over time. The combination of platinum with additional conductive and barrier layers allows the capacitor to operate reliably in high-temperature or high-stress environments, making it suitable for advanced semiconductor applications. The design also simplifies manufacturing by using standard deposition techniques compatible with existing semiconductor fabrication processes.
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October 23, 2017
December 3, 2019
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