A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of operation of a data processing system, the method comprising: receiving, from a processor of the data processing system at a cache controller of the data processing system, a first instruction to perform a first memory operation; indicating, by the cache controller, completion of the first instruction to the processor; initiating the first memory operation in the cache controller, including: writing a new entry for the first memory operation in an operation queue; storing metadata for the new entry; and recording an entry in a log, the entry indicating a status of the first memory operation, where the log, or a property of the log, is accessible by the processor; accessing an entry of the operation queue for an uninitiated second memory operation; initiating the second memory operation in a memory system via a memory interface in accordance with accessed entry; updating the metadata for the entry to indicate that the second memory operation has been initiated; providing, by the memory system to the cache controller, notification of completion of the second memory operation; responsive to receiving the notification of completion of the second memory operation: updating the entry in the log indicating the status of the second memory operation; updating metadata for the completed second memory operation to indicate that the second memory operation has been completed; and marking the entry in the operation queue, corresponding to the completed second memory operation, as non-valid.
This invention relates to a method for managing memory operations in a data processing system, particularly focusing on improving efficiency and visibility of memory operations between a processor and a cache controller. The problem addressed is the need for a processor to track the status of memory operations while minimizing latency and ensuring accurate completion reporting. The method involves a cache controller receiving a first memory operation instruction from a processor and immediately indicating completion to the processor, even though the operation may not yet be fully executed. The cache controller then initiates the first memory operation by writing a new entry into an operation queue, storing associated metadata, and recording an entry in a log that is accessible by the processor. The log provides the processor with visibility into the status of the operation. The cache controller also accesses an entry for an uninitiated second memory operation from the queue and initiates this operation in the memory system via a memory interface. Once initiated, the metadata for the second operation is updated to reflect this status. Upon receiving completion notification from the memory system, the cache controller updates the log entry and metadata to indicate completion and marks the corresponding queue entry as invalid. This approach allows the processor to receive early completion signals while ensuring accurate tracking of memory operations through the log and metadata, improving system efficiency and reliability.
2. The method of claim 1 , where the operation queue comprises a linked list stored in one or more linked blocks of a cache data array of the data processing system, the linked block having a tail block and a head block, and where writing the entry for the first memory operation in the operation queue comprises: accessing a tail pointer register to retrieve a block pointer to the tail block; accessing the tail block to determine if the tail block has a non-valid entry; if the tail block has a non-valid entry: updating the non-valid entry for the first memory operation; and if the tail block has no non-valid entry: updating a ‘next’ pointer in the tail block to point to a new tail block in the cache data array; and updating the tail pointer register to point to the new tail block.
This invention relates to a method for managing an operation queue in a data processing system, specifically for handling memory operations efficiently within a cache data array. The problem addressed is the need for a fast and scalable way to manage memory operations in a cache, ensuring efficient use of storage and minimizing latency. The operation queue is implemented as a linked list stored in one or more linked blocks of a cache data array. Each block in the linked list has a tail block and a head block. When writing an entry for a memory operation into the queue, the method first accesses a tail pointer register to retrieve a block pointer to the current tail block. The tail block is then checked to determine if it contains a non-valid entry. If a non-valid entry is found, it is updated with the new memory operation. If no non-valid entry exists, the method updates the ‘next’ pointer in the tail block to point to a new tail block in the cache data array and updates the tail pointer register to reflect this new tail block. This approach ensures that the queue dynamically expands as needed while maintaining efficient access and minimal overhead. The method optimizes cache utilization by reusing non-valid entries before allocating new blocks, reducing fragmentation and improving performance.
3. The method of claim 1 , where the operation queue comprises a linked list stored in one or more linked blocks of a cache data array of the data processing system, the linked blocks having a tail block and a head block, and where writing the new entry for the first memory operation in the operation queue comprises: accessing a head pointer register to retrieve a block pointer to the head block; accessing the head block to find a non-valid entry; updating the non-valid entry for the first memory operation; and marking the updated entry as ‘valid’ and ‘uninitiated’.
This invention relates to a method for managing an operation queue in a data processing system, specifically addressing efficient memory operation handling in a cache data array. The problem solved involves optimizing the storage and retrieval of memory operations to improve system performance and resource utilization. The operation queue is implemented as a linked list stored in one or more linked blocks within a cache data array. Each linked block contains entries for memory operations, and the queue is structured with a tail block and a head block. The head block is the primary location for writing new entries, while the tail block is used for reading completed operations. When a new memory operation is added to the queue, the method involves accessing a head pointer register to retrieve a block pointer that identifies the current head block. The head block is then accessed to locate a non-valid entry, which is an available slot for storing the new operation. The non-valid entry is updated with the details of the first memory operation, and the entry is marked as ‘valid’ and ‘uninitiated’ to indicate it is ready for processing but has not yet been started. This approach ensures efficient use of cache resources and minimizes latency in memory operation handling.
4. The method of claim 3 , further comprising, responsive to the notification of completion of the second memory operation: responsive to determining that all entries of the head block are marked as non-valid and the operation queue is not empty: updating the head pointer register to store a ‘next’ block pointer from head block, where the ‘next’ block pointer identifies a next block in the linked list.
This invention relates to memory management in computing systems, specifically addressing the challenge of efficiently handling memory operations in a linked list structure. The method involves managing a linked list of memory blocks, where each block contains entries that can be marked as valid or non-valid. The system monitors the completion of memory operations, such as read or write operations, and updates the head pointer of the linked list based on the validity of entries in the current head block. When a memory operation on a second block in the linked list is completed, the system checks whether all entries in the head block are marked as non-valid and whether the operation queue is not empty. If both conditions are met, the head pointer is updated to point to the next block in the linked list, identified by a ‘next’ block pointer stored in the head block. This ensures that the head of the linked list is always pointing to a block with valid entries, optimizing memory access and reducing latency. The method improves system performance by dynamically adjusting the head pointer based on the operational state of the memory blocks, ensuring efficient memory utilization and minimizing unnecessary access to invalid data.
5. The method of claim 1 , where the first memory operation comprises writing back, to the memory system, data stored in a first block in a cache data array of the data processing system.
This invention relates to data processing systems and memory management, specifically addressing the challenge of efficiently handling data transfers between a cache and a memory system. The method involves managing memory operations to optimize performance and resource utilization. A key aspect is writing back data from a cache data array to the memory system. This operation involves selecting a first block within the cache data array that contains data to be written back. The method ensures that the data stored in this block is transferred back to the memory system, maintaining data consistency and reducing unnecessary memory access. The process may include determining when to perform the write-back operation based on factors such as cache eviction policies, memory system availability, or system performance requirements. By efficiently managing these write-back operations, the system can improve overall data processing efficiency, reduce latency, and minimize power consumption. The invention is particularly useful in systems where frequent data transfers between cache and memory occur, such as in high-performance computing or embedded systems. The method ensures that data integrity is maintained while optimizing system resources.
6. The method of claim 5 , where the memory system comprises a persistent memory.
A method for managing data in a memory system that includes persistent memory addresses the challenge of efficiently handling data storage and retrieval in systems where persistent memory is used. Persistent memory retains data even when power is lost, but managing it requires specialized techniques to ensure data integrity and performance. The method involves tracking memory access patterns to optimize data placement and retrieval operations. It includes monitoring read and write operations to identify frequently accessed data regions, then dynamically adjusting memory allocation to prioritize these regions in persistent memory. This ensures that critical data is quickly accessible while minimizing wear on the persistent memory components. The method also incorporates error detection and correction mechanisms to maintain data reliability. By dynamically adapting to usage patterns, the system improves overall performance and longevity of the persistent memory. This approach is particularly useful in applications requiring high-speed data access with durability, such as enterprise storage systems or real-time data processing environments. The method ensures efficient use of persistent memory resources while maintaining data consistency and availability.
7. The method of claim 5 , where recording, by the cache controller, the entry indicating the status of the first memory operation in the log comprises storing in the log: a block pointer to the first block; an indication that said writing back, to the memory system, data stored in the first block has not yet been initiated; and an indication that said writing back, to the memory system, data stored in the first block has not yet been completed.
Data management in computer memory systems. A problem addressed is efficiently managing write-back operations for data blocks within a cache and the main memory system. This involves a cache controller and a log. The method comprises recording an entry in the log that signifies the status of a first memory operation. Specifically, this log entry includes a block pointer identifying the first block of data. Additionally, the log entry stores an indication that the process of writing back data stored in this first block to the memory system has not yet begun. Furthermore, the log entry includes an indication that the process of writing back data stored in the first block to the memory system has not yet been finished.
8. The method of claim 1 , further comprising: determining, from the first instruction, when the first memory operation is to be performed asynchronously.
A system and method for optimizing memory operations in a computing environment involves determining whether a memory operation should be performed asynchronously based on an instruction. The method includes analyzing the first instruction to identify whether the associated memory operation can be executed independently of the main processing flow, allowing for improved performance by overlapping memory access with other computations. The system may include a processor configured to execute instructions and a memory controller that manages memory operations. The memory controller evaluates the instruction to decide if the operation should be asynchronous, potentially reducing latency and increasing efficiency by allowing the processor to continue executing other tasks while the memory operation is in progress. This approach is particularly useful in systems where memory access is a bottleneck, enabling better utilization of processing resources. The method may also involve tracking dependencies between operations to ensure data consistency when performing asynchronous memory accesses. The overall goal is to enhance system performance by intelligently managing memory operations based on instruction characteristics.
9. The method of claim 1 , further comprising: receiving, from the processor at the cache controller, an asynchronous-store barrier (ASB) instruction; and responsive to receiving the ASB instruction from the processor, the cache controller tracking a completion status for memory operations corresponding to one or more first instructions received prior to the ASB instruction.
This invention relates to computer memory systems, specifically improving synchronization between a processor and a cache controller to ensure data consistency. The problem addressed is the need for efficient handling of memory operations in systems where a processor issues multiple instructions, some of which may involve asynchronous writes to memory. Without proper synchronization, subsequent operations may proceed before earlier writes are fully committed, leading to data inconsistencies. The invention provides a method for tracking the completion status of memory operations in response to an asynchronous-store barrier (ASB) instruction. When a processor sends an ASB instruction to a cache controller, the controller monitors the completion of all memory operations corresponding to instructions received before the ASB. This ensures that later instructions do not execute until prior writes are fully processed, maintaining data integrity. The method may also involve the cache controller signaling the processor once all tracked operations are complete, allowing the processor to proceed with subsequent tasks. This approach enhances system reliability by preventing race conditions and ensuring proper ordering of memory operations. The invention is particularly useful in high-performance computing environments where asynchronous operations are common.
10. A data processing system comprising: a processor; a memory system; a cache controller configured to provide an asynchronous interface between the processor and the memory system; and a cache accessible by the processor via the cache controller, where one or more first instructions, issued by the processor to the cache controller, for one or more first memory operations, are completed by the cache controller without blocking the processor, where the memory system is configured to send a notification of completion for a memory operation initiated by the cache controller, and where the cache controller is configured to track a completion status of memory operations of the one or more first memory operations, including: responsive to receiving a first instruction, from the processor, to perform a first memory operation: indicate completion of the first instruction to the processor, write a new entry for the first memory operation in an operation queue, store metadata for the new entry, and record an entry in a log, the entry indicating a status of the first memory operation, where the log, or a property of the log, is accessible by the processor, access an entry of the operation queue for an uninitiated second memory operation, initiate the second memory operation in the memory system in accordance with accessed entry, update metadata for the entry to indicate that the second memory operation has been initiated, receive, from the memory system, notification of completion of the second memory operation, responsive to receiving the notification of completion of the second memory operation: update the entry in the log indicating the status of the second memory operation, update metadata for the completed second memory operation to indicate that the second memory operation has been completed, and mark the entry in the operation queue, corresponding to the completed second memory operation, as non-valid.
Data processing systems. This invention addresses the problem of improving processor efficiency by reducing blocking during memory operations. A system includes a processor, a memory system, and a cache controller. The cache controller provides an asynchronous interface between the processor and a cache accessible by the processor. When the processor issues instructions for memory operations to the cache controller, these operations can be completed without blocking the processor. The memory system notifies the cache controller upon completion of a memory operation. The cache controller tracks the completion status of these operations. For a memory operation instruction from the processor, the cache controller indicates completion to the processor, adds the operation to an operation queue with associated metadata, and records its status in a log accessible by the processor. The cache controller then accesses uninitiated operations from the queue, initiates them in the memory system, updates their metadata to show initiation, and receives completion notifications from the memory system. Upon receiving a completion notification, the cache controller updates the log entry, marks the operation as completed in its metadata, and invalidates the corresponding entry in the operation queue.
11. The data processing system of claim 10 , where the memory system is configured to notify the cache controller when the first memory operation is complete.
A data processing system includes a memory system and a cache controller. The memory system performs memory operations, such as read or write operations, and the cache controller manages data caching between the memory system and a processor. The memory system is configured to notify the cache controller when a first memory operation is complete. This notification allows the cache controller to update its state or take further actions based on the completion of the memory operation. The system may also include a processor that executes instructions and generates memory access requests, which the cache controller processes. The cache controller may coordinate with the memory system to ensure data consistency and efficiency in memory operations. The notification mechanism ensures that the cache controller is aware of the completion status of memory operations, enabling proper synchronization and management of cached data. This system improves performance and reliability in data processing by ensuring timely updates and coordination between the memory system and the cache controller.
12. The data processing system of claim 10 , where the data processing system further comprises a data array, accessible by the cache controller, for storing the operation queue.
A data processing system includes a cache controller and a data array for managing an operation queue. The system is designed to improve data processing efficiency by optimizing the handling of operations in a computing environment. The cache controller manages data transfers between a cache memory and a main memory, ensuring that frequently accessed data is stored in the cache to reduce latency. The data array, accessible by the cache controller, stores the operation queue, which contains pending data operations such as read, write, or prefetch requests. By maintaining the operation queue in the data array, the system can efficiently prioritize and execute operations, reducing bottlenecks and improving overall system performance. The data array may be implemented as a dedicated memory structure or integrated within the cache controller, depending on the system architecture. This approach enhances data processing speed and resource utilization, particularly in high-performance computing environments where rapid access to cached data is critical. The system may also include additional components, such as a memory controller or a prefetch unit, to further optimize data flow and reduce latency. The operation queue stored in the data array allows the cache controller to dynamically adjust operation priorities based on system demands, ensuring efficient use of memory resources. This design is particularly useful in applications requiring real-time data processing, such as database management, high-frequency trading, or scientific computing.
13. The data processing system of claim 12 , where the data array is in the cache and where the data processing system further comprises: a head pointer register for storing a pointer to a head of the operation queue; and a tail pointer register for storing a pointer to a tail of the operation queue, where the head and tail pointers are accessible by the cache controller.
The invention relates to a data processing system designed to efficiently manage data operations in a cache memory. The system addresses the challenge of optimizing data access and processing by maintaining an operation queue within the cache, allowing for streamlined execution of data operations. The operation queue is managed using a head pointer register and a tail pointer register, both of which store pointers to the head and tail of the queue, respectively. These pointers are accessible by the cache controller, enabling dynamic tracking and updating of the queue's boundaries. The data array, which contains the data being processed, is also stored in the cache, ensuring low-latency access. The head and tail pointers facilitate efficient enqueueing and dequeueing of operations, reducing overhead and improving performance. The cache controller uses these pointers to manage the operation queue, ensuring that operations are processed in the correct order while minimizing cache access delays. This approach enhances the system's ability to handle concurrent data operations efficiently, particularly in high-performance computing environments where rapid data processing is critical.
14. The data processing system of claim 10 , where the completion status of the first memory operation is stored in the log, the data processing system further comprising: a data array comprising a plurality of blocks, where the log is stored in one or more blocks of the data array; and a first register for storing a block pointer to the one or more blocks of the data array that store the log, where the first register is accessible to the cache controller to enable the cache controller to access the log.
This invention relates to a data processing system designed to improve memory operation management by tracking completion status in a log stored within a data array. The system addresses the challenge of efficiently monitoring memory operations, particularly in scenarios where operations may fail or require retry, by maintaining a centralized log of operation statuses. The log is stored in one or more blocks of a data array, which is a structured storage component containing multiple blocks. A first register holds a block pointer that directs the system to the specific blocks storing the log, ensuring quick access. The cache controller, which manages data movement between memory and cache, can access this register to retrieve the log and verify operation completion statuses. This design enhances system reliability by providing a clear record of memory operations, allowing the system to handle errors and retries more effectively. The log's integration into the data array optimizes storage efficiency, while the dedicated register ensures fast access for the cache controller. This approach is particularly useful in systems where memory operations must be tracked and verified to maintain data integrity and performance.
15. The data processing system of claim 10 , where the memory system comprises a persistent memory.
A data processing system includes a memory system with persistent memory to improve data reliability and availability. The system processes data by storing it in the persistent memory, which retains information even when power is lost, ensuring data integrity during unexpected interruptions. The memory system may include additional components such as volatile memory for faster access and controllers to manage data storage and retrieval. The persistent memory is designed to handle frequent write operations while maintaining durability, addressing the problem of data loss in traditional volatile memory systems. The system may also include error correction mechanisms to detect and correct data corruption, further enhancing reliability. By integrating persistent memory, the system ensures that critical data remains accessible and intact, even in the event of power failures or system crashes. This approach is particularly useful in applications requiring high data durability, such as financial transactions, database management, and embedded systems where data loss can have significant consequences. The system may also include interfaces for connecting to external devices or networks, allowing seamless data transfer and synchronization. Overall, the use of persistent memory in the data processing system provides a robust solution for maintaining data integrity in various computing environments.
16. The data processing system of claim 15 , where an instruction set architecture of the data processing system comprises an instruction to clean data in the cache to the persistent memory.
A data processing system is designed to improve data management efficiency by integrating a specialized instruction for cache-to-persistent memory operations. The system includes a processor with a cache hierarchy and a persistent memory, where the persistent memory retains data even when power is lost. The processor executes instructions from an instruction set architecture (ISA) that includes a dedicated instruction to clean data from the cache to the persistent memory. This instruction ensures that modified data in the cache is written back to the persistent memory, maintaining data consistency and reliability. The system may also include additional features such as a memory controller to manage data transfers between the cache and persistent memory, and a power management unit to handle power-related operations. The cache may be organized into multiple levels, with the cleaning instruction targeting specific cache levels or the entire cache hierarchy. This approach reduces the risk of data loss during power failures and improves system reliability in applications requiring persistent storage, such as databases or file systems. The system may further include mechanisms to track dirty cache lines and prioritize data transfers based on system workload or power conditions.
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May 21, 2019
February 1, 2022
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