The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits also depends upon the value of the first sample.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A digital circuitry configured to calculate, from at least a value of a first sample of a first digital signal, a value of a second sample of a second digital signal, based on the value of the first sample, said value of the second sample having a second number of significant bits lower than a first number of significant bits of the value of the first sample, said second number of significant bits depending at least on the value of the first sample.
This invention relates to digital signal processing, specifically to circuitry that reduces the bit precision of a digital signal while dynamically adjusting the number of significant bits based on the input signal's value. The problem addressed is the need to efficiently reduce bit precision in digital signals while minimizing information loss, particularly in applications where fixed-point arithmetic is used and dynamic range adaptation is required. The circuitry processes a first digital signal with a first number of significant bits and generates a second digital signal with a second number of significant bits, where the second number is lower than the first. The reduction in bit precision is not fixed but depends on the value of the input sample, allowing for adaptive quantization. For example, if the input sample has a large magnitude, fewer bits may be retained, whereas a smaller magnitude may retain more bits to preserve detail. This dynamic adjustment helps maintain signal quality while reducing computational overhead and memory requirements. The circuitry can be implemented in hardware, such as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA), or in software running on a digital signal processor (DSP). The adaptive bit reduction is useful in applications like audio processing, sensor data compression, and real-time signal filtering, where both efficiency and signal integrity are critical. The invention ensures that the output signal retains sufficient precision for accurate reconstruction while optimizing resource usage.
2. The digital circuitry of claim 1 , wherein the second number of significant bits is defined according to the value the first sample, so that the second number of significant bits varies in a direction opposite to a direction of variation of an absolute value of the first sample.
This invention relates to digital signal processing, specifically to a method of dynamically adjusting the number of significant bits used in digital circuitry to represent signal samples. The problem addressed is the inefficiency of fixed-bit representations in digital systems, which either waste resources by using more bits than necessary for small signals or lose precision for large signals. The circuitry processes a digital signal comprising a sequence of samples, where each sample is represented by a first number of significant bits. The circuitry dynamically adjusts the number of significant bits used to represent a second sample based on the value of a first sample. Specifically, the second number of significant bits is inversely proportional to the absolute value of the first sample—meaning as the absolute value of the first sample increases, the number of significant bits decreases, and vice versa. This adaptive bit allocation ensures efficient use of digital resources while maintaining precision for small signals and reducing overhead for large signals. The circuitry may include a bit allocation module that determines the second number of significant bits based on the first sample's value. The adjustment can be applied to subsequent samples in the signal sequence, allowing for real-time adaptation to signal variations. This approach improves processing efficiency and reduces power consumption in digital systems handling variable-amplitude signals.
3. The digital circuitry of claim 2 , wherein the second number of significant bits is equal to a minimum of a first predefined number minus a rounding of a binary logarithm of the absolute value of the first sample, and a second predefined number.
The invention relates to digital circuitry for processing digital signals, specifically for optimizing the representation of signal samples to reduce computational complexity and memory usage. The problem addressed is the inefficient handling of signal samples with varying magnitudes, which can lead to unnecessary precision in digital processing systems, increasing resource requirements. The digital circuitry includes a processing unit configured to receive a first sample of a digital signal and determine a second number of significant bits for representing the sample. The second number of significant bits is calculated as the minimum of two values: a first predefined number minus a rounded binary logarithm of the absolute value of the first sample, and a second predefined number. This ensures that the number of significant bits is dynamically adjusted based on the sample's magnitude while enforcing a lower bound to prevent excessive bit reduction. The processing unit then processes the sample using the determined number of significant bits, improving efficiency in digital signal processing tasks such as filtering, modulation, or compression. The circuitry may also include memory for storing the processed samples and additional logic for further signal processing operations. The dynamic bit allocation reduces computational overhead and memory requirements without sacrificing signal integrity.
4. The digital circuitry of claim 2 , wherein the second number of significant bits is obtained using: a third predefined number lower than the bit depth of the first digital signal; a fourth predefined number higher than 1 and lower than the bit depth of the first digital signal minus the third predefined number; a fifth predefined number higher than or equal to 1, and lower than or equal to the bit depth of the first digital signal minus the third predefined number minus the fourth predefined number (D) plus 1; by: identifying the highest integer number between 0 and the fourth predefined number, for which the first integer number is lower than: two raised to the power of the bit depth of the first digital signal minus one; multiplied by two raised to the power of 1 minus the fifth predefined number minus said highest number; setting the second number of significant bits as the third predefined number plus said highest integer number.
This invention relates to digital signal processing, specifically to a method for determining a second number of significant bits in a digital signal. The problem addressed is efficiently selecting a subset of significant bits from a digital signal to optimize processing while maintaining signal integrity. The solution involves a multi-step mathematical approach to dynamically calculate the second number of significant bits based on predefined parameters. The process begins by defining three key parameters: a third predefined number, which is lower than the bit depth of the first digital signal; a fourth predefined number, which is higher than 1 and lower than the bit depth of the first digital signal minus the third predefined number; and a fifth predefined number, which is higher than or equal to 1 and lower than or equal to the bit depth of the first digital signal minus the third predefined number minus the fourth predefined number plus 1. The method then identifies the highest integer number between 0 and the fourth predefined number, ensuring that this integer is lower than a calculated threshold derived from the bit depth of the first digital signal. The threshold is determined by multiplying two raised to the power of the bit depth of the first digital signal minus one by two raised to the power of 1 minus the fifth predefined number minus the highest number. Finally, the second number of significant bits is set as the sum of the third predefined number and the highest integer number identified in the previous step. This approach ensures precise bit selection while maintaining computational efficiency.
5. The digital circuitry of claim 1 , wherein the second number of significant bits is defined according to a predicted difference between the value of the first sample and an approximation of the first sample using a third number of significant bits, so that the second number of significant bits varies in the same direction than the direction of variation of an absolute value of said predicted difference.
This invention relates to digital circuitry for processing digital signals, specifically improving the efficiency of digital-to-analog conversion or other signal processing tasks by dynamically adjusting the number of significant bits used in computations. The problem addressed is the trade-off between computational precision and resource usage, where fixed-bit representations either waste resources with excessive precision or introduce errors with insufficient precision. The circuitry processes a first digital sample of a signal, where the sample has a first number of significant bits. A second number of significant bits is dynamically determined based on a predicted difference between the sample's value and an approximation of the sample using a third number of significant bits. The second number of bits varies proportionally to the absolute value of this predicted difference—larger differences result in more bits, while smaller differences allow fewer bits. This adaptive approach optimizes precision where needed while reducing computational overhead elsewhere. The circuitry may include a predictor to estimate the difference, a bit allocator to adjust the second number of bits, and a processing unit to handle the sample with the dynamically allocated bits. The third number of bits is typically a fixed or pre-determined value used as a reference for the approximation. This method ensures efficient use of digital resources while maintaining signal integrity.
6. The digital circuitry of claim 5 , wherein the second number of significant bits is defined as a growing function of said predicted difference divided by the value of the first sample.
The invention relates to digital circuitry for processing signals, specifically improving the efficiency of digital signal processing by dynamically adjusting the number of significant bits used in computations. The problem addressed is the trade-off between computational accuracy and resource usage in digital systems, where fixed-bit representations may either waste resources by using more bits than necessary or lose precision by using too few. The digital circuitry includes a predictor that estimates a difference between a first sample and a subsequent sample in a signal. The circuitry then determines a second number of significant bits for processing the subsequent sample based on this predicted difference. The second number of significant bits is defined as a growing function of the predicted difference divided by the value of the first sample. This adaptive approach ensures that the number of bits allocated for processing dynamically adjusts according to the signal's characteristics, optimizing both accuracy and resource efficiency. The circuitry may also include a quantizer that processes the subsequent sample using the determined number of significant bits, further refining the signal representation. The overall system enhances digital signal processing by balancing precision and computational overhead, making it suitable for applications requiring real-time processing with limited resources.
7. The digital circuitry of claim 1 , wherein the second number of significant bits depends upon values of coefficients obtained by a frequency transform of a time window of samples of the first digital signal comprising the first sample.
The invention relates to digital signal processing, specifically to optimizing the bit precision of digital circuitry for efficient computation. The problem addressed is the computational inefficiency in digital signal processing systems where fixed bit precision is used, leading to unnecessary resource usage or degraded performance when processing signals with varying characteristics. The digital circuitry processes a first digital signal comprising a first sample and a second digital signal. The circuitry includes a first processing path for the first digital signal and a second processing path for the second digital signal. The first processing path includes a first multiplier and a first adder, while the second processing path includes a second multiplier and a second adder. The first multiplier multiplies the first digital signal by a first coefficient, and the first adder adds the result to a first accumulated value. The second multiplier multiplies the second digital signal by a second coefficient, and the second adder adds the result to a second accumulated value. The second processing path operates with a second number of significant bits that depends on the values of coefficients obtained by a frequency transform of a time window of samples of the first digital signal. This adaptive bit precision allows the circuitry to dynamically adjust its computational resources based on the signal characteristics, improving efficiency without sacrificing accuracy. The frequency transform, such as a Fourier transform, analyzes the signal to determine the optimal bit precision for processing, ensuring that only the necessary bits are used in subsequent computations. This approach reduces power consumption and computational overhead while maintaining signal integrity.
8. The digital circuitry of claim 1 , wherein the second number of significant bits is defined according to a value representative of a derivative of the first digital signal at the first sample.
The invention relates to digital signal processing, specifically to circuitry for processing digital signals with improved precision and efficiency. The problem addressed is the need to dynamically adjust the number of significant bits used in digital signal processing to balance computational accuracy and resource usage. Traditional fixed-bit processing either wastes resources by using excessive precision or introduces errors by using insufficient precision. The digital circuitry processes a first digital signal sampled at a first sample time. The circuitry includes a first processing path that processes the first digital signal using a first number of significant bits. A second processing path processes the first digital signal using a second number of significant bits, which is determined based on a value representative of the derivative of the first digital signal at the first sample. The derivative value indicates the rate of change of the signal, allowing the circuitry to adapt the precision dynamically. For example, if the derivative is small, fewer bits may be used without significant loss of accuracy, reducing computational overhead. Conversely, if the derivative is large, more bits are used to maintain accuracy. The circuitry may also include a comparator to compare the derivative value with a threshold, a selector to choose between the first and second processing paths based on the comparison, and a combiner to merge the outputs of the processing paths. This adaptive approach optimizes resource usage while preserving signal integrity, particularly in applications like audio processing, communications, or sensor data analysis where signal characteristics vary over time.
9. The digital circuitry of claim 8 , wherein the value representative of the derivative of the first digital signal at the first sample is an absolute difference between the value of the first sample and the value of the sample immediately preceding the first sample in the first digital signal.
The invention relates to digital signal processing, specifically to circuitry for computing derivatives of digital signals. The problem addressed is efficiently calculating the derivative of a digital signal in hardware, which is useful for applications like edge detection, signal analysis, and feature extraction. The circuitry processes a first digital signal composed of discrete samples and computes a value representing the derivative at a specific sample point. This derivative value is determined by taking the absolute difference between the value of the first sample and the value of the immediately preceding sample in the signal. This approach provides a simple yet effective way to approximate the derivative in digital systems, avoiding complex computations while maintaining accuracy for many practical applications. The circuitry may be part of a larger system that performs additional signal processing tasks, such as filtering or further derivative calculations. The method ensures real-time processing by leveraging basic arithmetic operations, making it suitable for embedded systems and high-speed digital signal processing.
10. The digital circuitry of claim 1 , wherein the value of the second sample is selected as a suitable value, belonging to an ordered set of suitable values, which is the closest to the value of the first sample in the ordered set of suitable values, and wherein the number of significant bits of each suitable value in the ordered set of suitable values is lower than the number of significant bits of any value in an open interval between said suitable value in the ordered set and an neighbor suitable value in said set.
This invention relates to digital circuitry for processing sampled data, particularly for reducing the bit width of digital samples while minimizing quantization error. The problem addressed is the trade-off between data precision and hardware efficiency, where reducing bit width can lead to significant quantization errors, especially in applications requiring high fidelity, such as audio processing or high-resolution signal analysis. The circuitry processes a first sample with a higher bit width and selects a second sample with a lower bit width from an ordered set of suitable values. The second sample is chosen as the closest suitable value to the first sample, ensuring minimal quantization error. The ordered set of suitable values is designed such that the number of significant bits in each value is lower than the number of bits in the open intervals between adjacent suitable values. This means the suitable values are spaced in a way that maintains precision where it matters most, while reducing overall bit width for efficiency. The approach ensures that the selected second sample retains as much meaningful information as possible from the original first sample, despite the reduced bit width. This is particularly useful in applications where hardware constraints limit the number of bits that can be processed efficiently, such as in real-time signal processing or embedded systems. The method balances precision and efficiency by strategically distributing the available bits to minimize distortion.
11. The digital circuitry of claim 1 , wherein: the value of the second sample is calculated based on an intermediary value, said intermediary value having a second number of significant bits lower than an intermediary number of significant bits of the intermediary value, and depending at least of said intermediary value; the intermediary value is calculated based on the value of the first sample, the intermediary number of significant bits being lower than the number of significant bits of the first sample.
This invention relates to digital circuitry for processing digital signals, specifically for reducing the bit width of digital samples while preserving signal integrity. The problem addressed is the computational and resource overhead associated with high-precision digital signal processing, where full bit-width operations are often unnecessary for maintaining signal quality. The circuitry processes a first digital sample with a certain number of significant bits and generates a second digital sample with fewer significant bits. The second sample's value is derived from an intermediary value, which itself has fewer significant bits than the intermediary value's original precision. The intermediary value is calculated from the first sample, but with reduced bit width compared to the first sample's original precision. This multi-stage reduction ensures that the final output retains sufficient accuracy while minimizing computational complexity and hardware resource usage. The intermediary value is computed by truncating or rounding the first sample to a lower bit width, and the second sample is then derived from this intermediary value, further reducing the bit width. This staged approach allows for efficient hardware implementation, as it avoids the need for high-precision arithmetic operations while still maintaining acceptable signal fidelity. The technique is particularly useful in applications where power efficiency and hardware simplicity are critical, such as in embedded systems or real-time signal processing.
12. The digital circuitry of claim 1 , wherein the second number of significant bits is selected among two or more candidate numbers of significant bits, each of said two or more candidate numbers of significant bits being lower than a first number of significant bits of the value of the first sample, and depending at least on the value of the first sample.
Digital circuitry processes digital signals by quantizing sample values to reduce bit width while minimizing distortion. The circuitry receives a first sample with a first number of significant bits and selects a second number of significant bits for quantization, where the second number is lower than the first. The selection is based on the value of the first sample and involves choosing among two or more candidate bit numbers, each lower than the original bit count. This adaptive quantization reduces computational complexity and memory usage while preserving signal quality. The circuitry may further process the quantized sample, such as applying a transformation or filtering, and may adjust the quantization dynamically based on subsequent samples or external parameters. The method ensures efficient signal processing with controlled distortion, suitable for applications like audio, image, or sensor data compression. The selection of candidate bit numbers may be predefined or determined algorithmically, optimizing performance for different signal characteristics.
13. The digital circuitry of claim 1 , wherein the second number of significant bits is lower than or equal to a number of significant bits allowing the second digital signal, or a signal derived therefrom to match an expected bit depth of a processing unit that receives as input said second digital signal, or a signal derived therefrom.
This invention relates to digital signal processing, specifically optimizing bit depth in digital circuitry to ensure compatibility with downstream processing units. The problem addressed is the mismatch between the bit depth of a digital signal and the expected bit depth of a processing unit, which can lead to inefficiencies, data loss, or processing errors. The solution involves digital circuitry that processes a first digital signal to generate a second digital signal with a reduced bit depth. The second digital signal, or a derived signal, is then adjusted to match the expected bit depth of the processing unit that will receive it. The key innovation is that the number of significant bits in the second digital signal is either lower than or equal to the number required to meet the processing unit's expected bit depth. This ensures that the signal is neither unnecessarily truncated nor padded, optimizing both data integrity and processing efficiency. The circuitry may include components for bit reduction, such as quantization or truncation, and may also include logic to dynamically adjust the bit depth based on the processing unit's requirements. This approach is particularly useful in systems where digital signals must be processed by multiple units with varying bit depth expectations, such as in audio processing, image processing, or telecommunications.
14. The digital circuitry of claim 1 , wherein the second number of significant bits is higher than or equal to a minimum number of significant bits of the value of the second sample that does not introduce a noticeable alteration in the second digital signal, or a signal derived therefrom.
This invention relates to digital signal processing, specifically to optimizing the number of significant bits used in digital circuitry to represent signal samples without introducing noticeable alterations. The problem addressed is the computational and storage inefficiency of using excessive bits for signal representation, which can lead to unnecessary resource consumption while not improving signal quality. The digital circuitry processes a first digital signal and a second digital signal, where each signal is composed of samples. The circuitry includes a bit reduction module that reduces the number of significant bits in the second digital signal based on a predefined criterion. The second number of significant bits is set to be higher than or equal to a minimum number of significant bits required to prevent noticeable alterations in the second digital signal or any derived signal. This ensures that the reduction in bit depth does not degrade the signal quality perceptibly. The bit reduction module may apply techniques such as quantization or truncation to achieve this reduction while maintaining signal integrity. The circuitry may also include a processing module that operates on the bit-reduced signal, ensuring efficient computation without compromising output quality. The invention aims to balance computational efficiency and signal fidelity by dynamically adjusting the bit depth based on the minimum required bits to avoid perceptible distortions.
15. The digital circuitry of claim 14 , wherein the noticeable alteration is a noticeable quantization noise.
The invention relates to digital circuitry designed to process signals, particularly focusing on introducing a noticeable alteration to the processed signal. The alteration is specifically a noticeable quantization noise, which is an audible or perceptible distortion introduced during digital signal processing. This quantization noise arises from the conversion of analog signals into digital form, where the discrete nature of digital representation introduces errors or noise. The circuitry is configured to generate or modify signals in a way that this quantization noise becomes perceptible, which may be useful in applications where such noise is intentionally introduced for artistic, diagnostic, or other purposes. The digital circuitry includes components for signal processing, such as analog-to-digital converters (ADCs), digital signal processors (DSPs), and digital-to-analog converters (DACs), which collectively contribute to the introduction of quantization noise. The circuitry may also include control mechanisms to adjust the level or characteristics of the quantization noise to achieve desired effects. This invention addresses the problem of managing or intentionally utilizing quantization noise in digital signal processing systems, where such noise is typically considered undesirable but may be leveraged for specific applications.
16. A digital circuitry configured to perform a convolution of an input digital signal, or a derivative thereof, and a second digital signal to obtain an output digital signal, a value of a second sample of the second digital signal being calculated from at least a value of a first sample of a first digital signal by a digital circuitry according to claim 1 .
This invention relates to digital signal processing, specifically to a system for performing convolution operations on digital signals. The problem addressed is the efficient computation of convolutions, which are fundamental in many signal processing applications such as filtering, correlation, and feature extraction. The system includes digital circuitry designed to convolve an input digital signal (or a modified version of it) with a second digital signal to produce an output digital signal. The second digital signal is generated by processing a first digital signal, where the value of a second sample in the second signal is derived from at least one sample of the first digital signal. This processing is performed by additional digital circuitry that applies a specific transformation, such as scaling, shifting, or other mathematical operations, to the first digital signal to produce the second digital signal. The convolution operation involves multiplying corresponding samples of the input signal and the second signal and summing the results over a defined window. The output signal is then generated based on these computations. The system is optimized for real-time or high-speed processing, ensuring efficient execution of convolution operations in digital signal processing applications. The design may be implemented in hardware, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), to achieve low-latency performance.
17. A non-transitory computer storage medium having stored thereon a second digital signal, wherein a value of a second sample of the second digital signal is calculated based on a value of a first sample of a first digital signal, said value of the second sample having a second number of significant bits lower than a first number of significant bits of the value of the first sample, said second number of significant bits depending at least on the value of the first sample.
This invention relates to digital signal processing, specifically to methods for reducing the bit depth of a digital signal while preserving signal quality. The problem addressed is the loss of information and degradation in signal quality when reducing the bit depth of a digital signal using conventional techniques, such as simple truncation or rounding, which can introduce distortion or artifacts. The invention provides a non-transitory computer storage medium storing a second digital signal derived from a first digital signal. The second digital signal has a reduced bit depth compared to the first digital signal, where the number of significant bits in the second signal depends on the value of the first signal. Specifically, the value of a second sample in the second digital signal is calculated based on the value of a first sample in the first digital signal, but with fewer significant bits. The reduction in bit depth is adaptive, meaning the number of significant bits retained in the second signal varies depending on the value of the first signal. This adaptive approach helps minimize quantization errors and distortion, particularly for signals with a wide dynamic range. The method ensures that higher-precision bits are retained for larger signal values, while smaller values may be represented with fewer bits, optimizing storage and processing efficiency without sacrificing signal fidelity.
18. A method to calculate, from at least a value of a first sample of a first digital signal, a value of a second sample of a second digital signal based on the value of the first sample, said value of the second sample having a second number of significant bits lower than a first number of significant bits of the value of the first sample, said second number of significant bits depending at least on the value of the first sample.
This invention relates to digital signal processing, specifically to methods for reducing the bit depth of a digital signal while preserving signal quality. The problem addressed is the loss of information and introduction of quantization noise when converting a high-bit-depth digital signal to a lower-bit-depth signal using conventional methods like truncation or rounding. The invention provides a method to calculate a lower-bit-depth sample of a second digital signal from a higher-bit-depth sample of a first digital signal, where the number of significant bits in the second sample dynamically adjusts based on the value of the first sample. This adaptive bit reduction minimizes quantization errors by allocating more bits to higher-amplitude samples and fewer bits to lower-amplitude samples, improving signal fidelity. The method ensures that the second sample retains meaningful precision relative to the first sample's magnitude, avoiding unnecessary bit loss in critical signal regions. The approach is particularly useful in applications requiring efficient data compression or hardware with limited bit-width processing capabilities while maintaining signal integrity. The technique can be applied in audio processing, sensor data compression, or any system where dynamic range reduction is needed without significant quality degradation.
19. A method of convolution of an input digital signal and a second digital signal to obtain an output digital signal, a value of a second sample of the second digital signal being calculated, from at least a value of a first sample of a first digital signal by a method according to claim 18 .
This invention relates to digital signal processing, specifically methods for convolving two digital signals to produce an output signal. The problem addressed is efficiently calculating samples of the second digital signal during convolution operations, which is computationally intensive in traditional approaches. The method involves convolving an input digital signal with a second digital signal to generate an output digital signal. A key aspect is calculating a value of a second sample of the second digital signal based on at least a value of a first sample of a first digital signal. The calculation method for the second sample involves generating a first digital signal by applying a first transformation to the input digital signal, then generating a second digital signal by applying a second transformation to the first digital signal. The second transformation is derived from the first transformation and a third transformation, which is applied to a third digital signal. The third digital signal is generated by applying a fourth transformation to the input digital signal. The transformations are selected to ensure the second digital signal can be efficiently computed while maintaining the integrity of the convolution operation. This approach reduces computational complexity by leveraging intermediate transformations, allowing for faster and more efficient convolution operations compared to direct methods. The method is particularly useful in applications requiring real-time signal processing, such as audio processing, image filtering, and communication systems.
20. A computer program product comprising computer code instructions stored on a non-transitory computer storage medium wherein the computer code instructions when executed by one or more processors configured the one or more processors to execute the method of claim 18 .
This invention relates to a computer program product for managing data processing tasks. The product includes computer code instructions stored on a non-transitory computer storage medium. When executed by one or more processors, these instructions configure the processors to perform a method for processing data. The method involves receiving a data processing request, determining whether the request meets predefined criteria, and if it does, executing a first set of operations. If the request does not meet the criteria, the method executes a second set of operations. The first set of operations may include tasks such as data validation, transformation, or aggregation, while the second set may involve error handling, logging, or alternative processing paths. The system dynamically adjusts the processing workflow based on the request's characteristics, ensuring efficient and accurate data handling. This approach optimizes resource usage and improves processing reliability by adapting to different types of requests. The invention is particularly useful in environments where data processing requirements vary, such as in cloud computing, enterprise systems, or real-time analytics platforms. The computer program product ensures flexibility and scalability in handling diverse data processing tasks.
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October 15, 2018
March 15, 2022
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