The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.
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2. The memory system of claim 1, wherein the center read sample corresponds to data read from the one or more memory devices using a center value corresponds to a first read level threshold, the left read sample corresponds to data read using a negative offset value that is lower than the center value, and right read sample corresponds to data read using a positive offset value that is higher than the center value.
This invention relates to memory systems, specifically improving data read accuracy in non-volatile memory devices such as flash memory. The problem addressed is the inherent variability in read operations due to factors like noise, wear, and process variations, which can lead to incorrect data retrieval. The solution involves a multi-level read sampling technique to enhance reliability. The memory system reads data from one or more memory devices using a center read level threshold, generating a center read sample. Additionally, it reads data using two offset thresholds: a left read sample with a negative offset below the center value and a right read sample with a positive offset above the center value. These three samples—center, left, and right—are used to improve data accuracy by providing redundant or complementary information. The offsets help account for variations in cell threshold voltages, reducing errors caused by noise or drift. The system may use these samples to apply error correction, adjust read thresholds dynamically, or select the most reliable data based on the sampled values. This approach enhances read reliability without requiring significant changes to the memory hardware, making it suitable for existing memory architectures.
3. The memory system of claim 1, wherein the first count operation counts a number of ones in the first value resulting from the first XOR operation, wherein the number of ones in the first value indicates a number of bits that have changed between the center read sample and the left read sample, wherein the second count operation counts a number of ones in the second value resulting from the second XOR operation, wherein the number of ones in the second value indicates a number of bits that have changed between the center read sample and the right read sample.
This invention relates to a memory system that compares read samples from a memory cell to determine bit changes. The system performs a first XOR operation between a center read sample and a left read sample, producing a first value. A first count operation then counts the number of ones in this first value, which indicates the number of bits that have changed between the center and left samples. Similarly, a second XOR operation is performed between the center read sample and a right read sample, generating a second value. A second count operation counts the number of ones in this second value, representing the number of bits that have changed between the center and right samples. The system uses these counts to analyze bit changes across multiple read samples, which can be useful for error detection, correction, or memory reliability assessment. The memory system may include additional components such as a memory controller, storage medium, and circuitry for performing the XOR and count operations. The invention helps identify discrepancies in read data, improving data integrity and reliability in memory operations.
4. The memory system of claim 1, wherein the processing device comprises a logic circuit to perform the first XOR operation and the second XOR operation.
A memory system includes a processing device that performs error correction operations on data stored in a memory array. The system addresses the challenge of efficiently detecting and correcting errors in stored data, particularly in high-density memory devices where data integrity is critical. The processing device includes a logic circuit designed to execute two XOR (exclusive OR) operations. The first XOR operation is used to generate a syndrome value from the stored data, which helps identify the location of errors. The second XOR operation is then applied to correct the detected errors based on the syndrome value. The logic circuit is optimized to perform these operations in parallel or sequentially, depending on the system requirements, to ensure fast and accurate error correction. This approach improves reliability by reducing the likelihood of uncorrected errors while maintaining high performance in memory access operations. The system is particularly useful in applications where data integrity is paramount, such as in enterprise storage, embedded systems, and high-reliability computing environments. The use of dedicated logic for XOR operations ensures low-latency error correction, making it suitable for real-time applications.
6. The memory system of claim 1, wherein the processing device is a NAND controller and the one or more memory devices are NAND memory devices.
A memory system includes a processing device and one or more memory devices, where the processing device manages data storage and retrieval operations for the memory devices. The system is designed to address challenges in memory management, such as optimizing performance, reliability, and efficiency in data handling. The processing device executes commands to read, write, and erase data in the memory devices, while also performing error detection and correction to ensure data integrity. The memory devices store data in a non-volatile manner, retaining information even when power is removed. The system may include additional features such as wear leveling to distribute write operations evenly across memory blocks, reducing wear and extending the lifespan of the memory devices. The processing device may also implement error correction codes (ECC) to detect and correct errors that occur during data storage or retrieval. In this specific configuration, the processing device is a NAND controller, and the memory devices are NAND memory devices. NAND controllers are specialized integrated circuits that manage the interface between a host system and NAND flash memory, handling tasks such as address translation, data buffering, and error management. NAND memory devices are non-volatile storage media that store data in arrays of memory cells, offering high density and cost-effective storage solutions. The system ensures reliable and efficient data storage by leveraging the capabilities of the NAND controller and NAND memory devices.
7. The memory system of claim 6, wherein the NAND controller performs a continuous read level calibration (cRLC) operation on the one or more memory device using the first difference bit count and the second difference count without sending the results from the center read sample, the left read sample, and the right read sample to an Error Correction Code (ECC) decoder.
This invention relates to memory systems, specifically improving read level calibration in NAND flash memory without relying on Error Correction Code (ECC) decoding. The problem addressed is the inefficiency of traditional read level calibration methods that require sending raw read samples to an ECC decoder for analysis, which consumes additional time and processing resources. The memory system includes a NAND controller and one or more memory devices. The NAND controller performs a continuous read level calibration (cRLC) operation to optimize read thresholds in the memory devices. During this operation, the controller obtains three read samples: a center read sample, a left read sample, and a right read sample. The controller then calculates a first difference bit count between the center and left samples and a second difference bit count between the center and right samples. These difference counts are used to adjust the read thresholds without sending the raw samples to an ECC decoder. This approach reduces latency and processing overhead by eliminating the need for ECC decoding during calibration. The method ensures accurate threshold adjustments while improving system performance.
8. The memory system of claim 7, wherein the first difference bit count exceeds a correction capability of the ECC decoder.
The invention relates to memory systems with error correction capabilities, specifically addressing scenarios where error correction fails due to excessive bit errors. In memory systems, error correction codes (ECC) are used to detect and correct bit errors that occur during data storage and retrieval. However, when the number of erroneous bits exceeds the correction capability of the ECC decoder, data recovery becomes impossible, leading to data loss or system failures. This invention improves reliability by handling such cases where the first difference bit count—the number of bit errors detected in a data block—exceeds the ECC decoder's correction threshold. The system includes a memory controller that monitors error rates and implements additional error mitigation techniques, such as adaptive error correction, data redundancy, or fallback mechanisms, to recover data even when the ECC decoder cannot correct all errors. The solution ensures data integrity and system stability in high-error environments, such as degraded storage media or harsh operating conditions. By dynamically adjusting error handling strategies based on the detected error magnitude, the system enhances fault tolerance and extends the lifespan of memory devices.
10. The memory system of claim 9, wherein the second center read sample corresponds to a second data read from the one or more memory devices using a second center value corresponding to a second read level threshold, the second left read sample corresponds to the second data read using a second negative offset that is lower than the second center value, and the second right read sample corresponds to the second data read using a second positive offset that is higher than the second center value.
This invention relates to memory systems, specifically improving data read accuracy in non-volatile memory devices such as flash memory. The problem addressed is the degradation of read accuracy due to variations in cell threshold voltages over time, which can lead to incorrect data retrieval. The solution involves a multi-level read operation that uses offset read levels to enhance reliability. The memory system performs a first read operation using a first center read level threshold to obtain initial data. To refine this data, a second read operation is conducted using a second center read level threshold, which may differ from the first. The second read operation generates three samples: a second center read sample, a second left read sample, and a second right read sample. The second center read sample is obtained by reading data at the second center value. The second left read sample is derived by applying a second negative offset below the second center value, while the second right read sample is obtained by applying a second positive offset above the second center value. These offset reads help distinguish between closely spaced threshold voltage distributions, improving data integrity. The system then processes these samples to correct errors and ensure accurate data retrieval. This method is particularly useful in high-density memory storage where read disturbances and wear are significant challenges.
11. The memory system of claim 9, wherein the center read sample and the second center read sample are performed concurrently, wherein the left read sample and the second left read sample are performed concurrently, and wherein the right read sample and the second right read sample are performed concurrently.
This invention relates to memory systems, specifically improving read operations in non-volatile memory devices. The problem addressed is the need for faster and more accurate data retrieval in memory systems, particularly when dealing with data stored in memory cells that may experience read disturbances or require multiple read operations to ensure accuracy. The memory system includes a controller configured to perform multiple read operations on memory cells to enhance data reliability. The controller executes a first read operation to obtain a center read sample from a target memory cell and a second read operation to obtain a second center read sample from the same cell. Additionally, the controller performs left and right read samples on adjacent memory cells to account for interference effects. The key innovation is that the center, left, and right read samples, along with their corresponding second samples, are performed concurrently. This concurrent execution reduces the overall time required for read operations while maintaining or improving data accuracy. The system may also include error correction mechanisms to further refine the read data based on the multiple samples obtained. By performing these operations in parallel, the memory system achieves faster read times without sacrificing reliability, making it particularly useful in high-performance storage applications.
12. The memory system of claim 10, wherein the first read level threshold and the second read level threshold correspond to a same page type.
The invention relates to memory systems, specifically addressing challenges in reading data from memory cells with different threshold voltage distributions. In non-volatile memory, such as flash memory, data is stored by adjusting the threshold voltage of memory cells, and reading data involves applying read level thresholds to distinguish between different voltage states. A common issue arises when memory cells of the same page type (e.g., single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC)) exhibit varying threshold voltage distributions due to factors like wear, temperature, or manufacturing variations. This can lead to read errors if the read level thresholds are not properly aligned with the actual voltage distributions. The invention provides a memory system that includes a controller configured to apply a first read level threshold and a second read level threshold to read data from memory cells of the same page type. The controller adjusts these thresholds based on the voltage distribution characteristics of the memory cells, ensuring accurate data retrieval even when the distributions shift over time. This approach improves read reliability and reduces errors in memory systems where memory cells of the same type may experience different voltage shifts. The system may also include error correction mechanisms to further enhance data integrity. The invention is particularly useful in high-density memory storage devices where maintaining precise read thresholds is critical for performance and longevity.
13. The memory system of claim 1, wherein the processing device resides in the one or more memory devices, and wherein the processing device is further to send the first difference bit count and the second difference bit count to a controller of the memory system.
This invention relates to memory systems, specifically addressing the need for efficient error detection and correction in memory devices. The system includes one or more memory devices and a processing device that resides within these memory devices. The processing device is configured to compare data stored in the memory devices with reference data to identify differences. It calculates a first difference bit count for a first memory device and a second difference bit count for a second memory device. These difference bit counts represent the number of differing bits between the stored data and the reference data in each respective memory device. The processing device then sends these difference bit counts to a controller of the memory system. The controller can use this information to assess data integrity, detect errors, or trigger corrective actions. The system may also include additional components, such as a host system interfacing with the memory devices and the controller, which manages data storage and retrieval operations. The processing device may further perform additional functions, such as generating error correction codes or validating data consistency across multiple memory devices. The overall goal is to enhance reliability and performance in memory systems by enabling real-time error detection and correction.
14. The memory system of claim 2, wherein the processing device uses a read sample offset (RSO) mask register to mask one or more read level thresholds of a page type and disable the first read level threshold, wherein the center read sample, the left read sample, and the right read sample are part of a RSO page read from a page that provides three-strobe results with bit error rate (BER) differences limited to the first read level threshold.
This invention relates to memory systems, specifically to techniques for improving read operations in non-volatile memory, such as flash memory, by dynamically adjusting read level thresholds to reduce bit error rates (BER). The problem addressed is the variability in read accuracy due to changes in memory cell characteristics over time, which can lead to higher BER when using fixed read thresholds. The system includes a processing device that controls read operations in a memory array. To mitigate BER issues, the processing device uses a read sample offset (RSO) mask register to selectively disable or adjust one or more read level thresholds for a specific page type. The RSO mask register allows the processing device to mask out certain read level thresholds, preventing their use during read operations. This is particularly useful for pages that require three-strobe read operations, where the processing device samples the memory cells at three different voltage levels (center, left, and right read samples) to obtain more accurate data. By disabling the first read level threshold via the RSO mask register, the system ensures that the three-strobe read results are only influenced by the remaining thresholds, which helps limit BER differences to an acceptable range. This approach improves read reliability without requiring complex calibration or additional hardware, making it suitable for high-density memory storage applications.
15. The memory system of claim 2, wherein the processing device uses a read sample offset (RSO) mask register to mask one or more read level thresholds of a page type and disable the first read level threshold and a second read level threshold, wherein the center read sample, the left read sample, and the right read sample are part of a RSO page read from a page that provides three-strobe results bit error rate (BER) differences limited to the first read level threshold and the second read level threshold.
This invention relates to memory systems, specifically improving read operations in non-volatile memory such as NAND flash. The problem addressed is optimizing read accuracy by dynamically adjusting read level thresholds to reduce bit error rates (BER) during data retrieval. The system includes a processing device that controls read operations in memory cells, particularly for pages storing data encoded with multiple read level thresholds. A key feature is the use of a read sample offset (RSO) mask register, which selectively masks or disables specific read level thresholds to refine the read process. The processing device can disable a first and second read level threshold while retaining others, allowing the system to focus on a center read sample and adjacent left and right read samples. These samples are part of an RSO page read, which generates three-strobe results that provide BER differences limited to the disabled thresholds. By masking these thresholds, the system reduces unnecessary read operations and improves accuracy by focusing on the most relevant data samples. This approach enhances reliability in memory systems where precise threshold adjustments are critical for error-free data retrieval.
17. The system of claim 16, wherein the memory sub-system further comprises a controller coupled to the one or more memory devices, wherein the processing device resides in the one or more memory devices, and wherein the subsequent operation comprises sending the right DBC and the left DBC to the controller.
The system relates to memory sub-systems, specifically addressing the challenge of efficiently managing data integrity and error correction in memory devices. The invention involves a memory sub-system with one or more memory devices and a controller coupled to these devices. A processing device, integrated within the memory devices, generates a right data bus code (DBC) and a left DBC for error detection or correction. The subsequent operation includes sending these DBCs to the controller, which processes them to ensure data reliability. The system may also include a host system interfacing with the memory sub-system, where the host system sends a command to the memory sub-system to initiate the generation and transmission of the DBCs. The processing device within the memory devices performs the necessary computations to produce the DBCs, which are then transmitted to the controller for further handling. This approach enhances data integrity by leveraging distributed processing within the memory devices while maintaining centralized control through the controller. The system is particularly useful in high-reliability applications where error detection and correction are critical.
18. The system of claim 16, wherein the memory sub-system further comprises a controller coupled to the one or more memory devices, wherein the processing device resides in the one or more memory devices, wherein the controller comprises an Error Correction Code (ECC) decoder, and wherein the subsequent operation is a continuous read level calibration (cRLC) operation using the right DBC and the left DBC without sending the right sample data, center sample data, and left sample data to the ECC decoder.
This invention relates to memory systems, specifically improving error correction and calibration processes in non-volatile memory devices. The system includes one or more memory devices and a memory sub-system with a controller. The controller is coupled to the memory devices and contains an Error Correction Code (ECC) decoder. A processing device, which may be part of the memory devices, executes operations to manage memory functions. The system performs a continuous read level calibration (cRLC) operation to optimize read thresholds for accurate data retrieval. During this calibration, the system uses right and left decision boundary calibration (DBC) values to adjust read levels without sending sample data (right, center, and left) to the ECC decoder. This reduces computational overhead and improves efficiency by avoiding unnecessary ECC decoding during calibration. The approach ensures reliable data integrity while minimizing processing time and resource usage. The system is particularly useful in high-density storage devices where frequent calibration is required to maintain performance and accuracy.
21. The method of claim 20, wherein the center read sample corresponds to data read from one or more memory devices using a first center value corresponds to a first read level threshold, the left read sample corresponds to data read using a negative offset value that is lower than the center value, and right read sample corresponds to data read using a positive offset value that is higher than the center value.
This invention relates to memory read operations, specifically improving data reliability in non-volatile memory devices by using multiple read samples with offset thresholds. The problem addressed is the inherent variability in memory cell read operations, which can lead to errors due to noise, wear, or other disturbances. The solution involves reading data from memory cells using three distinct read levels: a center value, a left offset value below the center, and a right offset value above the center. The center read sample is obtained using a first read level threshold, while the left and right read samples are obtained using thresholds offset negatively and positively from the center value, respectively. This multi-level sampling technique enhances error detection and correction by providing additional data points for comparison, allowing the system to more accurately determine the intended stored value. The method is particularly useful in flash memory and other non-volatile storage technologies where read disturbances and cell degradation are common challenges. By analyzing the three read samples, the system can better distinguish between correct data and corrupted or noisy readings, improving overall data integrity.
22. The method of claim 20, wherein performing the first XOR operation and the second XOR operation comprises performing the first XOR operation and the second XOR operation by a processing device of a memory sub-system, wherein performing the first count operation and the second count operation comprises performing the first count operation and the second count operation by the processing device of the memory system, and wherein the method further comprises outputting the difference bit count to a host system coupled to the memory sub-system.
This invention relates to memory sub-systems and methods for efficiently comparing data stored in memory. The problem addressed is the computational overhead and latency associated with comparing large datasets in memory, particularly when verifying data integrity or detecting errors. The solution involves a processing device within the memory sub-system performing XOR operations and count operations to determine the difference between two datasets. The processing device executes a first XOR operation between a first dataset and a second dataset, followed by a second XOR operation between the first dataset and a third dataset. The processing device then performs a first count operation to count the number of differing bits in the result of the first XOR operation and a second count operation to count the differing bits in the result of the second XOR operation. The difference between these two counts is calculated, and this difference bit count is output to a host system coupled to the memory sub-system. This approach offloads the comparison workload from the host system, reducing latency and improving efficiency in memory operations. The method is particularly useful in applications requiring frequent data comparisons, such as error detection, data validation, or consistency checks in storage systems.
23. The method of claim 20, wherein performing the first XOR operation and the second XOR operation comprises performing the first XOR operation and the second XOR operation by a processing device of a memory sub-system, and wherein performing the first count operation and the second count operation comprises performing the first count operation and the second count operation by a host system coupled to the memory sub-system.
This invention relates to a method for error detection in data storage systems, specifically involving XOR operations and bit counting to identify errors in data stored in a memory sub-system. The method addresses the challenge of efficiently detecting errors in data stored across multiple memory devices, such as in a redundant array of independent disks (RAID) configuration, where data integrity is critical. The method involves performing a first XOR operation on data stored in a first set of memory devices within the memory sub-system. This operation generates a first result, which is then used to perform a first count operation to determine the number of set bits (bits with a value of 1) in the first result. Similarly, a second XOR operation is performed on data stored in a second set of memory devices, producing a second result. A second count operation is then performed to determine the number of set bits in the second result. The processing device within the memory sub-system executes the XOR operations, while the host system coupled to the memory sub-system performs the count operations. By comparing the results of these operations, the system can detect discrepancies that indicate potential data corruption or errors. This approach distributes computational tasks between the memory sub-system and the host system, optimizing performance and reliability in data storage environments.
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August 18, 2021
May 14, 2024
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