An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step and a ρ step of the SHA calculation, a third section to perform a χ step of the SHA calculation and a fourth section to perform a τ step of the SHA calculation.
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2. The apparatus of claim 1, wherein first round SHA datapath comprises 320 processing elements, each of which processes five (5) bits of data, to form a 1600 bit data width pipeline.
This invention relates to cryptographic processing, specifically a high-throughput SHA (Secure Hash Algorithm) datapath architecture. The problem addressed is the need for efficient, parallelized processing of large data widths in cryptographic hash functions, particularly for SHA-1, which requires handling 1600-bit data widths. Traditional implementations often suffer from bottlenecks due to sequential processing or inefficient parallelization. The apparatus includes a first round SHA datapath composed of 320 processing elements, each configured to process 5 bits of data simultaneously. This parallel structure enables a 1600-bit data width pipeline, significantly increasing throughput by distributing the workload across multiple processing elements. The design ensures that each processing element operates independently on its assigned 5-bit segment, allowing for concurrent computation of the entire 1600-bit data width. This architecture is particularly suited for high-performance cryptographic applications where rapid hash computation is critical, such as in network security, data integrity verification, and digital signatures. The parallel processing approach minimizes latency and maximizes efficiency, making it advantageous over serial or less granular parallel implementations. The invention may also include additional rounds or stages of SHA processing, though the focus here is on the first round's datapath configuration.
3. The apparatus of claim 2, wherein the 320 processing elements are arranged into the three groups of processing elements comprising a first group of processing elements, a second group of processing elements, and a third group of processing elements.
This invention relates to a parallel processing apparatus designed to enhance computational efficiency in high-performance computing systems. The apparatus includes 320 processing elements organized into three distinct groups: a first group, a second group, and a third group. Each group is configured to handle specific computational tasks, allowing for parallel processing and improved throughput. The arrangement of processing elements into these groups enables efficient task distribution, load balancing, and inter-group communication, which are critical for optimizing performance in complex computing environments. The apparatus is particularly suited for applications requiring high-speed data processing, such as scientific simulations, machine learning, and real-time analytics. By dividing the processing elements into three groups, the system can simultaneously execute multiple operations, reducing latency and increasing overall computational capacity. This modular design also facilitates scalability, allowing the apparatus to adapt to varying workload demands without significant reconfiguration. The invention addresses the challenge of efficiently managing large-scale parallel processing tasks by providing a structured and flexible architecture that maximizes resource utilization and minimizes bottlenecks.
5. The apparatus of claim 1, wherein the three groups of processing elements implement three separate time-redundant SHA calculations.
The invention relates to a cryptographic processing apparatus designed to enhance security and reliability in computing systems. The apparatus includes multiple processing elements organized into three distinct groups, each group performing a separate time-redundant Secure Hash Algorithm (SHA) calculation. SHA is a widely used cryptographic hash function for data integrity and security, but traditional implementations are vulnerable to transient faults or attacks. By using three separate groups of processing elements, the apparatus performs redundant SHA calculations at different times, ensuring that any errors or tampering in one calculation can be detected and corrected by comparing results from the other groups. This time-redundant approach improves fault tolerance and resistance to transient errors, such as those caused by radiation or electrical noise, while also mitigating the risk of malicious interference. The apparatus may be integrated into systems requiring high-security cryptographic operations, such as financial transactions, secure communications, or authentication protocols. The redundant calculations allow for cross-verification, ensuring the integrity of the hash output even if one or more processing elements fail or are compromised. This design is particularly useful in environments where reliability and security are critical, such as aerospace, defense, or high-performance computing.
8. The apparatus of claim 7, wherein the parity calculation is computed using at least one of a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, or a Reed-Solomon code.
This invention relates to error detection and correction in data storage or transmission systems, specifically addressing the need for efficient and reliable parity calculations to ensure data integrity. The apparatus includes a parity calculation module that computes parity information for data blocks to detect and correct errors during storage or transmission. The parity calculation is performed using at least one of a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, or a Reed-Solomon code. These error-correcting codes are selected based on their ability to detect and correct different types of errors, such as single-bit errors (Hamming), multiple-bit errors (BCH), or burst errors (Reed-Solomon). The apparatus may also include a data encoding module that prepares data for storage or transmission by applying the selected error-correcting code, and a data decoding module that reconstructs the original data by detecting and correcting errors using the parity information. The system ensures robust data integrity in applications where errors are likely, such as in high-speed communication networks, solid-state storage devices, or optical storage media. The use of multiple error-correcting code options allows the apparatus to be adapted to different error profiles and performance requirements.
11. The electronic device of claim 10, wherein first round SHA datapath comprises 320 processing elements, each of which processes five (5) bits of data, to form a 1600 bit data width pipeline.
This invention relates to cryptographic processing, specifically a high-throughput SHA (Secure Hash Algorithm) datapath architecture for electronic devices. The problem addressed is the need for efficient, parallelized cryptographic computations to meet performance demands in modern security applications. The invention describes an electronic device incorporating a first-round SHA datapath with 320 processing elements. Each processing element handles 5 bits of data, enabling a 1600-bit data width pipeline. This parallel structure allows simultaneous processing of multiple data segments, significantly increasing throughput compared to serial implementations. The datapath is optimized for SHA-1 or SHA-2 algorithms, where the first round of hashing operations is computationally intensive. By distributing the workload across 320 elements, the design minimizes latency and maximizes efficiency in hardware implementations. The architecture may be integrated into ASICs, FPGAs, or other programmable logic devices for applications requiring high-speed cryptographic operations, such as network security, data encryption, or authentication systems. The invention improves upon prior art by leveraging fine-grained parallelism at the bit level, reducing the number of clock cycles required per hash operation.
12. The electronic device of claim 11, wherein the 320 processing elements are arranged into the three groups of processing elements comprising a first group of processing elements, a second group of processing elements, and a third group of processing elements.
This invention relates to electronic devices with specialized processing architectures, particularly for parallel processing tasks. The device includes a processing system with 320 processing elements organized into three distinct groups. The first group of processing elements is configured to handle a specific subset of computational tasks, while the second group is optimized for a different subset. The third group operates independently to manage additional processing requirements. Each group may have unique configurations or optimizations tailored to their respective tasks, allowing the device to efficiently distribute workloads across the processing elements. This grouping improves performance by enabling parallel execution of different types of operations, reducing bottlenecks, and enhancing overall computational efficiency. The arrangement ensures that tasks are processed in an optimized manner, leveraging the strengths of each group to maximize throughput and minimize latency. The device is particularly useful in applications requiring high-performance parallel processing, such as data analytics, machine learning, or real-time signal processing.
14. The electronic device of claim 10, wherein the three groups of processing elements implement three separate time-redundant SHA calculations.
The invention relates to electronic devices with enhanced security features, specifically focusing on secure hash algorithm (SHA) computations. The problem addressed is ensuring the integrity and reliability of cryptographic operations in electronic devices, particularly in environments where hardware faults or tampering could compromise security. The solution involves a system where multiple processing elements perform redundant SHA calculations to detect and correct errors, improving fault tolerance and security. The electronic device includes a plurality of processing elements organized into three distinct groups. Each group independently executes a SHA calculation, producing three separate results. These redundant computations allow the device to cross-verify the outputs, ensuring that any discrepancies due to faults or attacks are detected. The device compares the results from the three groups and identifies any mismatches, which may indicate errors or tampering. If a majority of the results agree, the device proceeds with the consensus output, effectively mitigating the impact of a single faulty or compromised group. This approach enhances the reliability of cryptographic operations, making the device more resilient to hardware failures and malicious interference. The system is particularly useful in high-security applications where data integrity is critical.
15. The electronic device of claim 14, further comprising: an output register to receive an output of the three separate time-redundant SHA calculations and a parity calculation.
The invention relates to electronic devices implementing secure cryptographic operations, specifically focusing on enhancing the reliability of Secure Hash Algorithm (SHA) computations. The problem addressed is the potential for errors in cryptographic calculations due to transient faults or hardware malfunctions, which could compromise security. The solution involves performing three separate time-redundant SHA calculations to detect and correct errors. Each SHA calculation is executed independently, and the results are compared to identify discrepancies. Additionally, a parity calculation is performed to further verify the integrity of the computations. The output register receives the results of these three SHA calculations and the parity calculation, allowing the device to determine the correct output by consensus or error detection. This redundancy ensures that even if one or two of the SHA calculations produce incorrect results due to faults, the correct result can still be identified. The system improves the reliability of cryptographic operations in electronic devices, particularly in safety-critical or high-security applications where data integrity is paramount.
17. The electronic device of claim 16, wherein the parity calculation is computed using at least one of a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, or a Reed-Solomon code.
This invention relates to electronic devices that implement error detection and correction in data storage or transmission systems. The problem addressed is ensuring data integrity by detecting and correcting errors that may occur during storage or transmission. The device includes a memory controller configured to perform parity calculations on data to be stored or transmitted. The parity calculation is computed using at least one of a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, or a Reed-Solomon code. These error-correcting codes are used to generate redundancy information that allows the device to detect and correct errors in the data. The memory controller may also include a parity check module to verify the integrity of the stored or transmitted data by comparing the computed parity with the stored or received parity information. If errors are detected, the error-correcting code is used to reconstruct the original data. The device may further include a storage medium or a communication interface for transmitting the data. The use of these error-correcting codes ensures reliable data storage and transmission by mitigating the effects of noise, interference, or hardware failures.
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December 23, 2020
May 14, 2024
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