A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.
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2. The memory of claim 1, wherein the feedback device is further configured to adjust the first reading circuit in response to the at least one first bit having a first bit value, and to adjust the second reading circuit in response to the at least one first bit having a second bit value different from the first bit value.
This invention relates to memory systems with adaptive read circuits for improving data integrity. The problem addressed is the variability in memory cell behavior due to manufacturing imperfections, wear, or environmental factors, which can lead to read errors. The solution involves a memory system with multiple reading circuits and a feedback mechanism that dynamically adjusts these circuits based on stored configuration data. The memory system includes at least two reading circuits, each optimized for different conditions. A feedback device monitors the output of these circuits and uses stored configuration bits to determine which circuit is performing optimally. If the configuration bits indicate a first state, the feedback device adjusts the first reading circuit to improve its performance. If the configuration bits indicate a second state, the feedback device adjusts the second reading circuit instead. This adaptive approach ensures that the most suitable reading circuit is used for each memory access, reducing errors and improving reliability. The configuration bits may be stored in a dedicated register or within the memory array itself. The feedback device can adjust parameters such as voltage levels, timing, or reference signals in the reading circuits. This dynamic adjustment compensates for variations in memory cell characteristics over time, enhancing the overall robustness of the memory system. The invention is particularly useful in high-density or high-reliability memory applications where traditional static read circuits may fail to account for environmental or aging effects.
3. The memory of claim 1, wherein the feedback device is further configured to adjust a resistance of the at least one of the first reading circuit or the second reading circuit to adjust a voltage level of the first node.
The invention relates to memory systems, specifically to a memory device with adjustable reading circuits for improving data read operations. The problem addressed is ensuring accurate and reliable data reading from memory cells, particularly in systems where voltage levels at internal nodes may vary due to process, voltage, or temperature variations. The solution involves a memory device with a feedback mechanism that dynamically adjusts the resistance of reading circuits to stabilize the voltage level at a critical node, enhancing read accuracy. The memory device includes a first reading circuit and a second reading circuit connected to a first node, which is linked to a memory cell. The feedback device monitors the voltage at the first node and adjusts the resistance of at least one of the reading circuits to maintain the desired voltage level. This adjustment compensates for variations in operating conditions, ensuring consistent read performance. The feedback device may include circuitry to detect voltage deviations and control resistive elements within the reading circuits to fine-tune the voltage. The invention improves reliability in memory read operations by dynamically compensating for environmental and manufacturing-induced variations.
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March 26, 2022
May 28, 2024
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