Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.
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2. The method of claim 1, wherein one or more registers of the memory device are configured to store the one or more predetermined poisoned bit locations.
A method for managing memory errors in a computing system involves identifying and handling predetermined poisoned bit locations within a memory device. The memory device includes one or more registers configured to store the locations of these poisoned bits, which are known error-prone or defective memory locations that may cause data corruption or system failures. The method detects access attempts to these poisoned bit locations during read or write operations. Upon detection, the system prevents access to these locations, either by redirecting the operation to an alternative memory location or by generating an error signal to notify the system of the attempted access. This approach ensures data integrity by avoiding interactions with unreliable memory regions, thereby reducing the risk of system crashes or data corruption. The registers storing the poisoned bit locations can be dynamically updated to reflect changes in memory health over time, allowing the system to adapt to new errors as they arise. This method is particularly useful in systems where memory reliability is critical, such as in high-performance computing, embedded systems, or environments with stringent fault tolerance requirements.
3. The method of claim 1, wherein the one or more predetermined poisoned bit locations are indicated to the memory device through one or more commands to program a register of the memory device transmitted from the host device to the memory device, prior to receiving the command.
This invention relates to memory systems, specifically methods for managing poisoned bits in memory devices. The problem addressed is the need to efficiently identify and handle corrupted or unreliable data bits (poisoned bits) in memory storage to prevent errors during data retrieval. The method involves a host device communicating with a memory device to preemptively mark specific bit locations as poisoned before data operations occur. The host device sends one or more commands to the memory device to program a register within the memory device, where these commands specify the locations of the poisoned bits. This register programming step occurs before the memory device receives any subsequent commands for data operations, such as read or write commands. By pre-marking these locations, the memory device can avoid using or misinterpreting corrupted data during later operations, improving data integrity and reliability. The method ensures that the memory device is aware of unreliable bit locations in advance, allowing it to take corrective actions, such as error correction or data bypass, without disrupting normal memory operations. This approach is particularly useful in systems where certain memory cells are prone to corruption due to wear, manufacturing defects, or environmental factors. The register programming step is a key aspect, as it enables dynamic and flexible management of poisoned bits without requiring physical modifications to the memory hardware.
9. The method of claim 8, wherein detecting the one or more errors in the second data set is based, at least in part, on comparing the first group of ECC check bits with the second group of ECC check bits.
This invention relates to error detection in data storage systems, specifically using error-correcting code (ECC) check bits to identify discrepancies between data sets. The problem addressed is ensuring data integrity by detecting errors in stored or transmitted data, particularly when comparing two data sets to verify consistency. The method involves generating a first group of ECC check bits for a first data set and a second group of ECC check bits for a second data set. The second data set may be a copy, a transmitted version, or a retrieved version of the first data set. Errors in the second data set are detected by comparing the first and second groups of ECC check bits. If the check bits differ, it indicates that one or more errors exist in the second data set. This comparison can be performed using standard ECC algorithms, such as parity checks, Hamming codes, or other error-detection techniques. The method may also include additional steps, such as correcting detected errors if possible or flagging the data for further review. The comparison of ECC check bits provides a reliable way to verify data integrity without requiring a full bit-by-bit comparison of the entire data sets, which can be computationally expensive. This approach is particularly useful in systems where data redundancy or transmission reliability is critical, such as in memory systems, storage devices, or communication networks.
15. The method of claim 14, wherein inverting the one or more bits of the first data set corresponds to inverting the one or more bits of the first data set read from the memory array, after comparing the first group of ECC check bits with the second group of ECC check bits.
This invention relates to error correction in memory systems, specifically improving reliability by selectively inverting data bits based on error detection. The method addresses the problem of data corruption in memory arrays by using error-correcting code (ECC) to identify and correct errors. The system reads a first data set from a memory array and generates a first group of ECC check bits from this data. A second group of ECC check bits is generated from the same data after a potential error event, such as a read operation or a retention period. The two groups of ECC check bits are compared to determine if an error has occurred. If an error is detected, the method inverts one or more bits of the first data set to correct the error. This inversion is performed after the comparison of the ECC check bits, ensuring that the correction is based on the detected discrepancy. The technique enhances data integrity by leveraging ECC to identify and resolve bit-level errors efficiently, particularly in memory systems prone to soft errors or retention failures. The method may be applied in various memory technologies, including DRAM, flash, or other storage media where error correction is critical.
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December 19, 2022
June 4, 2024
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