A computer processor with control and data processing capabilities comprises a decode unit for decoding instructions. A data processing facility comprises a first data execution path including fixed operators and a second data execution path including at least configurable operators, the configurable operators having a plurality of predefined configurations, at least some of which are selectable by means of an opcode portion of a data processing instruction. The decode unit is operable to detect whether a data processing instruction defines a fixed data processing operation or a configurable data processing operation, said decode unit causing the computer system to supply data for processing to said first data execution path when a fixed data processing instruction is detected and to said configurable data execution path when a configurable data processing instruction is detected.
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1. A hardware computer processor having control and data processing capabilities, said computer processor comprising: a hardware decode unit for decoding instructions and operable to separate control instructions from data processing instructions thereby to supply all control instructions and no data processing instructions to a dedicated hardware control processing facility; the dedicated hardware control processing facility comprising a control execution path dedicated to processing only said control instructions, said control execution path having its own control register file of a first bit width for handling control instructions of a first bit width and functional units comprising a branch unit, a hardware execution unit, and a load/store unit; and a dedicated hardware data processing facility dedicated to processing said data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register file, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes; wherein said decode unit is operable to supply one of said control instructions to one of said functional units and operable to detect whether one of said data processing instructions defines a fixed data processing instruction or a configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand, said decode unit causing the computer processor to supply said one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; and wherein said controller is operable to configure the connectivity of said configurable operators in accordance with configuration information provided in the opcode portion of said configurable data processing instruction, and wherein said configurable operators are arranged to receive said at least one operand.
A computer processor has separate control and data processing units. The control unit handles control instructions using its own registers and execution paths, dealing with tasks like branching and memory access. The data processing unit, separate from the control unit, uses wider registers and handles data instructions. It contains two data execution paths: one with fixed operations, and another with configurable operators. The configurable operators are pre-configured into classes selectable via instruction opcodes. The processor decodes instructions, sending control instructions to the control unit and data instructions to the appropriate data path (fixed or configurable) based on the opcode. A controller configures the configurable operators' connections based on the opcode.
2. A computer processor according to claim 1 , wherein the decode unit is capable of decoding a stream of instruction packets from memory, each packet comprising a plurality of instructions.
The computer processor from the previous description can decode a stream of instruction packets retrieved from memory, where each packet contains multiple instructions. The decode unit processes these packets to identify and separate control and data instructions, routing them to the respective processing units as described before, using instruction opcodes to determine the specific operation and destination data path.
3. A computer processor according to claim 1 , wherein the decode unit is operable to detect if an instruction packet contains a data processing instruction.
The computer processor from the first description contains a decode unit which identifies whether an instruction packet contains data processing instructions, allowing for efficient routing of different instruction types to the appropriate execution units. This detection mechanism enables the separation of control and data processing, ensuring optimized execution for each type of instruction.
4. A computer processor according to claim 1 , wherein the configurable operators are configurable at the level of multibit values.
In the computer processor of the first description, the configurable operators can be configured at the level of multi-bit values, enabling a flexible range of operations. The configuration is determined by the instruction opcode, allowing the processor to adapt to different data processing needs by manipulating data at a granular level.
5. A computer system according to claim 4 , wherein the configurable operators are configurable at the level of words.
Building upon the previous claim, the configurable operators in the data processing unit can be configured at the level of entire words. This allows for the manipulation of larger data units, enhancing the processor's capability to handle complex calculations and data transformations within the configurable data path, determined by the opcode.
6. A computer processor according to claim 1 , wherein a plurality of the fixed operators of the first data execution path is arranged to perform a plurality of fixed operations in independent lanes according to single instruction multiple data principles.
In the computer processor described initially, the fixed operators in the first data execution path are arranged to perform several fixed operations in independent lanes, following the Single Instruction Multiple Data (SIMD) principle. This allows the processor to execute the same operation on multiple data elements simultaneously, accelerating fixed data processing tasks.
7. A computer processor according to claim 1 , wherein a plurality of configurable operators of the second data execution path is arranged to perform multiple operations in different lanes according to single instruction multiple data principles.
Extending the SIMD capability to the second data execution path, the configurable operators are also arranged to perform multiple operations in different lanes simultaneously. This increases the flexibility of the processor, enabling parallel processing of configurable operations on multiple data streams.
8. A computer processor according to claim 1 , wherein configurable operators of the second data execution path are arranged to receive configuration information which determines the nature of the operations performed.
The configurable operators in the second data execution path receive configuration information that determines the specific nature of the operations they perform. This configuration data allows the operators to adapt to various data processing tasks dynamically, based on the instruction.
9. A computer processor according to claim 8 , wherein configurable operators of the second execution path are arranged to receive configuration information which determines the nature of the operations performed from said opcode portion of the configurable data processing instruction.
In the computer processor, the configurable operators receive configuration information directly from the opcode portion of the configurable data processing instruction. This allows the opcode to control the behavior of the configurable operators.
10. A computer processor according to claim 1 , wherein interconnectivity between two or more of said configurable operators of the second data execution path is controlled by configuration information.
The interconnectivity between two or more of the configurable operators in the second data execution path can be controlled by configuration information provided in the opcode. This allows for complex data flows and dependencies to be established between the operators, enabling sophisticated computations.
11. A computer processor according to claim 1 , wherein at least one configurable operator of the second data execution path is capable of executing data processing instructions with an execution depth greater than two computations before returning results to a results store.
At least one configurable operator in the second data execution path can execute data processing instructions with an execution depth greater than two computations before returning results. This enables complex, multi-stage computations to be performed within a single operator, minimizing data transfer overhead.
12. A computer processor according to claim 1 , comprising a switch mechanism for receiving results from one or more of said configurable operators and switching the results as appropriate for supply to one or more of a result store and feed back loop.
The computer processor contains a switch mechanism that receives results from the configurable operators and routes them either to a result store or back into a feedback loop. This enables iterative calculations and complex data processing pipelines within the configurable data path.
13. A computer processor according to claim 1 , comprising a plurality of control maps for mapping configuration bits received from configurable data processing instructions to configuration information for supply to configurable operators of the second data execution path.
The computer processor incorporates multiple control maps for translating configuration bits from the configurable data processing instructions into configuration information used by the configurable operators. These maps provide a flexible and efficient way to manage the complex configuration requirements of the operators.
14. A computer processor according to claim 1 , comprising a switch mechanism for receiving configuration information from a control map and switching it as appropriate for supply to configurable operators of the second data execution path.
A switch mechanism is present to receive configuration information from a control map and route it to specific configurable operators. This allows for dynamic and adaptable configurations of the data processing path.
15. A computer processor according to claim 1 , comprising configurable operators selected from one or more of: multiply accumulate operators; arithmetic operators; state operators; and cross-lane permuters.
The configurable operators can be selected from a variety of functional units, including multiply-accumulate operators, arithmetic operators, state operators, and cross-lane permuters. This diverse set of operators provides a wide range of data processing capabilities within the configurable data path.
16. A computer processor according to claim 1 , comprising operators and an instruction set capable of performing one or more operations selected from: Fast Fourier Transforms; Inverse Fast Fourier Transforms; Viterbi encoding/decoding; Turbo encoding/decoding; and Finite Impulse Response calculations; and any other Correlations or Convolutions.
The computer processor includes operators and an instruction set capable of performing operations such as Fast Fourier Transforms (FFTs), Inverse Fast Fourier Transforms (IFFTs), Viterbi encoding/decoding, Turbo encoding/decoding, Finite Impulse Response (FIR) calculations, correlations, and convolutions. The processor is designed for signal processing and related applications.
17. A method of operating a computer processor having control and data processing capabilities, said computer processor comprising a decode unit for decoding instructions; a dedicated control processing facility comprising a control execution path dedicated to processing only control instructions, said control execution path having its own control register file of a first bit width for handling control instructions of a first bit width and functional units comprising a branch unit, an execution unit, and a load/store unit; and a dedicated data processing facility dedicated to processing data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register file, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes, the method comprising: separating, with said decode unit, control instructions from data processing instructions thereby supplying all control instructions and no data processing instructions to the dedicated control processing facility; supplying, by said decode unit, one of said control instructions to one of said functional units; decoding a plurality of instructions to detect whether at least one of said data processing instructions of said plurality of instructions defines a fixed data processing instruction or a configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand; causing the computer processor to supply said at least one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; configuring the connectivity of said configurable operators in accordance with configuration information provided in said opcode portion of said configurable data processing instruction, wherein said configurable operators are arranged to receive said at least one operand; and outputting results produced by said first data execution path when a fixed data processing instruction is detected and outputting results produced by said second data execution path when a configurable processing instruction is detected.
A method for operating a computer processor with separate control and data processing units, involving: decoding instructions; separating control and data instructions; directing control instructions to a dedicated control unit with its own registers and execution path; directing data instructions to a data processing unit with wider registers and two execution paths (fixed and configurable operators); decoding data instructions to identify fixed or configurable operations based on opcodes; routing data instructions to the appropriate data path; configuring the configurable operators' connections according to the opcode; receiving operands by the configurable operators; and outputting results from either data path based on the instruction type.
18. A hardware computer processor having control and data processing capabilities, said computer processor comprising: a hardware decode unit for decoding instructions and operable to separate control instructions from data processing instructions thereby to supply all control instructions and no data processing instructions to a dedicated hardware control processing facility; the dedicated hardware control processing facility comprising a control execution path dedicated to processing only said control instructions, said control execution path having its own control register file of a first bit width for handling control instructions of a first bit width and functional units, comprising a branch unit, a hardware execution unit, and a load/store unit; a dedicated hardware data processing facility dedicated to processing said data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register file, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes; and a switch mechanism for receiving data processing operands from a configurable data processing instruction and switching them as appropriate for supply to one or more of said configurable operators; wherein said decode unit is operable to supply one of said control instructions to one of said functional units and operable to detect whether one of said data processing instructions defines a fixed data processing instruction or said configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand, said decode unit causing the computer processor to supply said one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; and wherein said controller is operable to configure the connectivity of said configurable operators in accordance with configuration information provided in the opcode portion of said configurable data processing instruction, and wherein said configurable operators are arranged to receive said at least one operand.
A computer processor with separate control and data processing units. It includes a decode unit separating control and data processing instructions, routing control instructions to a control unit with dedicated registers and execution paths. Data processing instructions are routed to a separate data processing unit with wider registers and two data execution paths (fixed and configurable operators). A switch mechanism directs data processing operands to the configurable operators. The decode unit detects fixed or configurable operations based on opcodes. A controller configures the configurable operators based on the opcode, enabling flexible data processing.
19. A hardware computer processor having control and data processing capabilities, said computer processor comprising: a hardware decode unit for decoding instructions and operable to separate control instructions from data processing instructions thereby to supply all control instructions and no data processing instructions to a dedicated hardware control processing facility; the dedicated hardware control processing facility comprising a control execution path dedicated to processing only said control instructions, said control execution path having its own control register file of a first bit width for handling control instruction of a first bit width and functional units comprising a branch unit, a hardware execution unit, and a load/store unit; and a dedicated hardware data processing facility dedicated to processing said data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register file, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes, wherein said configurable operators are configurable at the level of multibit values comprising four or more bits; wherein said decode unit is operable to supply one of said control instructions to one of said functional units and operable to detect whether one of said data processing instructions defines a fixed data processing instruction or a configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand, said decode unit causing the computer processor to supply said one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; and wherein said controller is operable to configure the connectivity of said configurable operators in accordance with configuration information provided in the opcode portion of said configurable data processing instruction, and wherein said configurable operators are arranged to receive said at least one operand.
A computer processor includes separate control and data processing units. A decode unit separates control instructions (sent to a dedicated control unit) from data processing instructions (sent to a dedicated data processing unit). The data processing unit has wider registers and two data execution paths: one with fixed operators, the other with configurable operators configurable at the level of multibit values (four or more bits). A controller configures the configurable operators based on the opcode of the configurable data processing instruction.
20. A hardware computer processor having control and data processing capabilities, said computer processor comprising: a hardware decode unit for decoding instructions and operable to separate control instructions from data processing instructions thereby to supply all control instructions and no data processing instructions to a dedicated hardware control processing facility; the dedicated hardware control processing facility comprising a control execution path dedicated to processing only said control instructions, said control execution path having its own control register file of a first bit width for handling control instructions of a first bit width and functional units comprising a branch unit, a hardware execution unit, and a load/store unit; a dedicated hardware data processing facility dedicated to processing said data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes and arranged to receive configuration information which determines the nature of the operations to be performed; and a control map associated with said configurable operators of the second execution path, said control map being operable to receive at least one configuration bit from a configurable data processing instruction and to provide configuration information to the configurable operators responsive thereto; wherein said decode unit is operable to supply one of said control instructions to one of said functional units and operable to detect whether one of said data processing instructions defines a fixed data processing instruction or said configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand, said decode unit causing the computer processor to supply said one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; and wherein said controller is operable to configure the connectivity of said configurable operators in accordance with said configuration information provided in the opcode portion of said configurable data processing instruction, and wherein said configurable operators are arranged to receive said at least one operand.
A computer processor has separate control and data processing units. Control instructions are sent to a dedicated control unit, while data processing instructions are sent to a dedicated data processing unit. The data processing unit has wider registers and two data execution paths (fixed and configurable operators). The configurable operators are pre-configured and receive configuration information to determine their behavior. A control map translates configuration bits from configurable data processing instructions into configuration information for the configurable operators. The decode unit detects the instruction type, and the controller configures the configurable operators based on the instruction's opcode.
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March 31, 2004
July 9, 2013
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