A semiconductor device is disclosed. A conductive pillar for electrically connecting a semiconductor die to a circuit board may be gradually slimmed from the semiconductor die to the circuit board. A dummy conductive layer may be disposed between the semiconductor die and the conductive pillar. A width of an opening for opening a pattern of the circuit board may range from about 50% to 90% of the width of the lower end of the conductive pillar. Accordingly, a mechanical stress is prevented from being transmitted from the conductive pillar to the semiconductor die, or is absorbed by the dummy conductive layer, and thus, preventing cracks of the semiconductor die and a dielectric layer having a low dielectric constant.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a semiconductor die comprising a bond pad; a conductive pillar coupled to the bond pad of the semiconductor die; a circuit board coupled to the conductive pillar, wherein a width of the conductive pillar gradually decreases from an upper end of the conductive pillar at the semiconductor die to a lower end of the conductive pillar at the circuit board; and a dummy conductive layer between the bond pad and the semiconductor die.
A semiconductor device includes a semiconductor die with a bond pad. A conductive pillar connects to the bond pad and extends to a circuit board. The pillar's width gradually decreases from the top (at the die) to the bottom (at the circuit board). A dummy conductive layer exists between the bond pad and the semiconductor die, potentially absorbing stress and preventing cracks. This tapered pillar design, along with the dummy layer, reduces mechanical stress on the die.
2. The semiconductor device of claim 1 , wherein the semiconductor die comprises a dielectric layer having a dielectric constant of about 4 or less.
The semiconductor device described above also uses a semiconductor die containing a dielectric layer. This dielectric layer has a low dielectric constant of approximately 4 or less. The purpose of the low dielectric constant is to improve the electrical performance of the die by reducing capacitance and signal propagation delays.
3. The semiconductor device of claim 1 further comprising a protective layer having an opening therein, wherein an upper center region of the upper end passes through the opening to be directly connected to the bond pad, and wherein the protective layer is between an upper periphery of the upper end and the bond pad.
The semiconductor device described in the first claim further includes a protective layer with an opening. The top center of the conductive pillar passes through this opening, directly connecting to the bond pad. The protective layer is positioned between the upper edges of the conductive pillar and the bond pad, shielding the edges and adding to the stress-reduction by controlling the area of direct contact.
4. The semiconductor device of claim 1 , wherein the circuit board comprises: a circuit pattern; and a solder mask, wherein the solder mask has an opening to allow the circuit pattern to be connected to the conductive pillar, and wherein the opening of the solder mask has a width greater than a width of the lower end of the conductive pillar.
In the semiconductor device above, the circuit board includes a circuit pattern and a solder mask. The solder mask has an opening allowing the circuit pattern to connect to the conductive pillar. The solder mask opening is wider than the bottom of the conductive pillar. The wider opening provides space for a robust solder connection while minimizing stress at the join.
5. The semiconductor device of claim 4 , wherein a solder is disposed between the conductive pillar and the circuit pattern.
In the semiconductor device of the previous description, solder is placed between the conductive pillar and the circuit pattern. This solder electrically and mechanically connects the pillar to the circuit pattern on the circuit board. The solder ensures reliable electrical contact and provides mechanical support.
6. A semiconductor device comprising: a semiconductor die comprising a bond pad; a conductive pillar coupled to the bond pad of the semiconductor die; a circuit board coupled to the conductive pillar, wherein a width of the conductive pillar gradually decreases from an upper end of the conductive pillar at the semiconductor die to a lower end of the conductive pillar at the circuit board; and a dummy conductive layer between the bond pad and the conductive pillar.
A semiconductor device has a semiconductor die with a bond pad. A conductive pillar is attached to the die's bond pad and is connected to a circuit board. The conductive pillar's width decreases gradually from the top (near the die) to the bottom (near the circuit board). A dummy conductive layer exists between the bond pad and the conductive pillar. This structure helps distribute stress and prevent damage to the semiconductor die.
7. The semiconductor device of claim 6 wherein a width of the dummy conductive layer is greater than a width of the upper end of the conductive pillar.
In the semiconductor device described above, the dummy conductive layer's width is greater than the width of the top of the conductive pillar. The wider dummy layer further enhances stress distribution by increasing the contact area and providing a larger buffer between the pillar and the die.
8. The semiconductor device of claim 6 further comprising a protective layer having an opening therein, wherein an upper center region of the upper end passes through the opening to be directly connected to the dummy conductive layer, and wherein the protective layer is between an upper periphery of the upper end and the dummy conductive layer.
The semiconductor device above also includes a protective layer with an opening. The upper center of the conductive pillar passes through the opening and connects directly to the dummy conductive layer. The protective layer is positioned between the upper edges of the conductive pillar and the dummy conductive layer. This setup shields the edges and controls the contact area, reducing stress.
9. The semiconductor device of claim 6 wherein the entire upper end of the conductive pillar is directly connected to the dummy conductive layer.
In the semiconductor device from claim 6, the entire top surface of the conductive pillar is directly connected to the dummy conductive layer. This full connection provides maximum electrical contact and helps distribute stress evenly across the interface between the pillar and the dummy layer.
10. A semiconductor device comprising: a semiconductor die; a conductive pillar coupled to the semiconductor die; and a circuit board coupled to the conductive pillar, wherein a width of the conductive pillar gradually increases from an upper end of the conductive pillar at the semiconductor die to a lower end of the conductive pillar at the circuit board, wherein the circuit board comprises: a circuit pattern; and a solder mask, wherein the solder mask has an opening to allow the circuit pattern to be connected to the conductive pillar, and wherein the opening of the solder mask has a width smaller than a width of the lower end of the conductive pillar.
A semiconductor device includes a semiconductor die, a conductive pillar, and a circuit board. The conductive pillar's width gradually increases from the top (near the die) to the bottom (near the circuit board). The circuit board has a circuit pattern and a solder mask. The solder mask includes an opening allowing the circuit pattern to be connected to the conductive pillar, but the opening's width is smaller than the conductive pillar's bottom.
11. The semiconductor device of claim 10 , wherein the width of the opening of the solder mask ranges from about 50% to about 90% of the width of the lower end of the conductive pillar.
The semiconductor device above has a solder mask opening with a width that ranges from about 50% to about 90% of the conductive pillar's bottom width. This specific range allows sufficient solder contact while controlling the solder joint's shape and preventing bridging to adjacent components.
12. The semiconductor device of claim 10 , wherein a solder is disposed between the conductive pillar and the circuit board, the solder completely filling the opening of the solder mask.
The semiconductor device previously described has solder placed between the conductive pillar and the circuit board. The solder completely fills the solder mask opening. This complete fill ensures a strong electrical and mechanical connection and also provides additional structural support.
13. A semiconductor device comprising: a semiconductor die; a conductive pillar coupled to the semiconductor die; a circuit board coupled to the conductive pillar, wherein a width of the conductive pillar gradually increases from an upper end of the conductive pillar at the semiconductor die to a lower end of the conductive pillar at the circuit board; and a dummy conductive layer disposed between the semiconductor die and the conductive pillar.
A semiconductor device includes a semiconductor die, a conductive pillar connected to the die, and a circuit board connected to the pillar. The conductive pillar increases in width from top (at the die) to bottom (at the circuit board). A dummy conductive layer is located between the semiconductor die and the conductive pillar, buffering the connection.
14. The semiconductor device of claim 13 , wherein the semiconductor die comprises a bond pad, and the dummy conductive layer is disposed between the bond pad and the conductive pillar.
The semiconductor device mentioned above has a semiconductor die with a bond pad. The dummy conductive layer sits between the bond pad and the conductive pillar. This placement cushions the connection, absorbing stress and preventing damage.
15. The semiconductor device of claim 13 , wherein the semiconductor die comprises a bond pad, and the dummy conductive layer is disposed between the bond pad and the semiconductor die.
The semiconductor device outlined above contains a semiconductor die that includes a bond pad. The dummy conductive layer is positioned between the bond pad and the semiconductor die itself. This strategic placement is designed to mitigate stress and prevent cracking within the die material.
16. A semiconductor device comprising: a semiconductor die comprising: a bond pad; and a protective layer having an opening formed therein; a conductive pillar comprising an upper end comprising an upper center region coupled to the bond pad, wherein the protective layer is between an upper periphery of the upper end of the conductive pillar and the bond pad; a circuit board; a solder coupling a lower end of the conductive pillar to the circuit board; and a dummy conductive layer coupled to the bond pad.
A semiconductor device includes a semiconductor die which has a bond pad and a protective layer with an opening. A conductive pillar's upper center connects to the bond pad, with the protective layer between the pillar's upper edges and the bond pad. The conductive pillar is connected at its lower end with a solder to a circuit board. A dummy conductive layer is also coupled to the bond pad. This design is intended to reduce stress and prevent cracking.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 16, 2011
July 23, 2013
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