A semiconductor device includes: a semiconductor chip having a switching element and multiple pads electrically connected to the switching element; and multiple lead terminals electrically connected to the respective pads. The multiple lead terminals include a control terminal used for control of on/off operation of the switching element, and a main terminal into which a main current flows when the switching element is in an on state. A coupling coefficient k falls within a range of −3%≦k≦2%, where the coupling coefficient k is defined by a parasitic inductance Lg in a current path of a control current flowing in the control terminal, a parasitic inductance Lo in a current path of the main current, and a mutual inductance Ms of the parasitic inductances Lg and Lo.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
2. The semiconductor device according to claim 1 , wherein when an x-direction, a y-direction orthogonal to the x-direction, and a z-direction orthogonal to an xy-plane defined by the x-direction and the y-direction are defined, the first terminal and the second terminal are spaced apart from each other on a same plane along the xy-plane, and the third terminal and the fourth terminal are arranged at different z-coordinates from each other, and adjacent to each other without a gap when being positively projected onto the xy-plane.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. The device's first and second terminals are on the same plane (x-y plane) and are separated. The third and fourth terminals have different z-coordinates (heights), are adjacent to each other with no gap when projected onto the x-y plane.
3. The semiconductor device according to claim 1 , wherein when an x-direction, a y-direction orthogonal to the x-direction, and a z-direction orthogonal to an xy-plane defined by the x-direction and the y-direction are defined, the third terminal and the fourth terminal are spaced apart from each other on a same plane along the xy-plane, and the first terminal and the second terminal are arranged at different z-coordinates from each other, and adjacent to each other without a gap when being positively projected onto the xy-plane.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. The third and fourth terminals are on the same plane (x-y plane) and are separated. The first and second terminals have different z-coordinates (heights), are adjacent to each other with no gap when projected onto the x-y plane.
4. The semiconductor device according to claim 1 , wherein when an x-direction, a y-direction orthogonal to the x-direction, and a z-direction orthogonal to an xy-plane defined by the x-direction and the y-direction are defined, the first terminal and the second terminal are spaced apart from each other on a same plane along the xy-plane, and the third terminal and the fourth terminal are arranged at different z-coordinates from each other, and overlap with each other when being positively projected onto the xy-plane.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. The device's first and second terminals are on the same plane (x-y plane) and are separated. The third and fourth terminals have different z-coordinates (heights), and overlap each other when projected onto the x-y plane.
5. The semiconductor device according to claim 1 , wherein when an x-direction, a y-direction orthogonal to the x-direction, and a z-direction orthogonal to an xy-plane defined by the x-direction and the y-direction are defined, the third terminal and the fourth terminal are spaced apart from each other on a same plane along the xy-plane, and the first terminal and the second terminal are arranged at different z-coordinates from each other, and overlap with each other when being positively projected onto the xy-plane.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. The third and fourth terminals are on the same plane (x-y plane) and are separated. The first and second terminals have different z-coordinates (heights), and overlap each other when projected onto the x-y plane.
6. The semiconductor device according to claim 1 , further comprising a plurality of bonding wires electrically connecting the plurality of pads with the corresponding lead terminals, wherein when an x-direction, a y-direction orthogonal to the x-direction, and a z-direction orthogonal to an xy-plane defined by the x-direction and the y-direction are defined, the third terminal and the fourth terminal are spaced apart from each other in the x-direction on a same plane along the xy-plane, and extend from the semiconductor chip in the y-direction, and the first terminal and the second terminal are arranged on a same plane along the xy-plane, and the bonding wires connecting the first terminal and the second terminal with the corresponding pads intersect with each other on at least one location when the bonding wires are positively projected onto the xy-plane.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. Bonding wires connect the pads and lead terminals. The third and fourth terminals are spaced apart in the x-direction on the same x-y plane and extend from the chip in the y-direction. The first and second terminals are on the same x-y plane. The bonding wires connecting the first and second terminals to their pads intersect when projected onto the x-y plane.
7. The semiconductor device according to claim 1 , wherein the switching element is an insulated gate bipolar transistor, the first terminal is a gate terminal electrically connected to a gate of the insulated gate bipolar transistor, the second terminal is a Kelvin emitter terminal electrically connected to an emitter of the insulated gate bipolar transistor, the third terminal is an emitter terminal electrically connected to an emitter of the insulated gate bipolar transistor, and the fourth terminal is a collector terminal electrically connected to a collector of the insulated gate bipolar transistor.
The semiconductor device includes a semiconductor chip with a switching element and multiple pads connected to it, along with lead terminals connected to the pads. These terminals include a control terminal for switching the element on/off, and a main terminal carrying the main current when the element is on. The coupling coefficient 'k' is between -3% and 2%, where 'k' is calculated using parasitic inductance (Lg) in the control current path, parasitic inductance (Lo) in the main current path, and mutual inductance (Ms) of Lg and Lo. The switching element is an insulated gate bipolar transistor (IGBT). The first terminal is a gate terminal connected to the IGBT's gate, the second terminal is a Kelvin emitter terminal connected to the IGBT's emitter. The third terminal is an emitter terminal connected to the IGBT's emitter, and the fourth terminal is a collector terminal connected to the IGBT's collector.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 16, 2014
March 14, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.