Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.
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1. A method for forming a semiconductor package comprising: providing a package substrate, wherein the package substrate comprises first and second major surfaces and a die region on the first surface thereof; processing the first surface of the substrate, wherein the processed first surface of the substrate comprises protruded portions corresponding to conductive traces and a plurality of recesses between the conductive traces; processing the second surface of the substrate to form via contacts and a plurality of recesses between the via contacts; providing a stiffener at least at non-die region of the package substrate, wherein the stiffener is provided below and in direct contact with the conductive traces which are directly coupled to and in direct contact with contact pads disposed on the first surface of the package substrate; providing a first dielectric layer and filling the recesses between the conductive traces with the first dielectric layer, wherein the first dielectric layer isolates the conductive traces; providing a second dielectric layer and filling the recesses between the via contacts with the second dielectric layer, wherein the second dielectric layer isolates the via contacts; providing a die having a sensing element; attaching the die on the die region; electrically coupling the die to the contact pads that are disposed on the first surface of the package substrate and are directly coupled to the conductive traces by insulated wire bonds; and providing a cap over the first surface of the package substrate, wherein the cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds, and wherein the insulated wire bond comprises first and second ends, wherein the first end is bonded to die pad of the die while the second end is bonded to the contact pad, the insulated wire bond comprises a conductive wire and an outer coating surrounding the conductive wire, wherein the outer insulator coating covers and extends to about the entire length of the conductive wire except at portions which are bonded to the die pad and contact pad, and the insulated wire bonds are directly exposed to an environment through at least one access port of the package.
A method for building a semiconductor package involves starting with a package substrate that has a top and bottom surface, and a designated area for a chip on the top. The top surface is prepared with raised conductive traces and recessed areas between them. The bottom surface is prepared with via contacts and recessed areas between them. A stiffener is attached to the bottom surface, making direct contact with the conductive traces on top. A first insulating material fills the recessed areas between the conductive traces, isolating them. A second insulating material fills the recessed areas between the via contacts, isolating them. A chip with a sensing element is attached to the designated area. The chip is connected to contact pads on the substrate's top surface using insulated wires, where the wire insulation covers the entire wire except for the bonding points. A cap is placed over the top surface, creating an enclosed space housing the chip and wires. The insulated wires are exposed to the outside environment through at least one opening in the package.
2. The method of claim 1 wherein: the cap comprises a top portion and sidewalls; and the access port extends through inner and outer surfaces of the top portion of the cap.
Building upon the semiconductor package method, the cap that covers the chip and wires consists of a top and side walls. The opening in the package, through which the insulated wires are exposed to the environment, passes through both the inner and outer surfaces of the top of the cap.
3. The method of claim 1 wherein: attaching the die is performed after providing a second dielectric layer.
Building upon the semiconductor package method, attaching the chip with the sensing element to the substrate's top surface happens after the second insulating material has been applied to the bottom surface containing the via contacts.
4. The method of claim 1 wherein: attaching the die is performed prior to processing the second surface of the substrate.
Building upon the semiconductor package method, attaching the chip with the sensing element to the substrate's top surface occurs before preparing the bottom surface with via contacts and recessed areas.
5. The method of claim 4 comprising: wherein the second dielectric layer is provided after providing the stiffener.
Building upon the semiconductor package method where the chip is attached before bottom surface preparation, the second insulating material that fills the recessed areas around the via contacts is applied after attaching the stiffener to the substrate's bottom.
6. The method of claim 5 wherein: the stiffener partially extends to the die region of the package substrate; and the stiffener is provided after processing the second surface of the substrate and prior to providing the second dielectric layer.
Building upon the method where the second insulating layer is provided after the stiffener, the stiffener extends partially underneath the chip area. Also, the stiffener is attached after the substrate's bottom surface is prepared with via contacts, but before the second insulating material is applied to the bottom surface.
7. The method of claim 1 wherein the first and second dielectric layers are separate dielectric layers.
Building upon the semiconductor package method, the insulating material used to isolate the conductive traces on the top surface (first dielectric layer) is a different material than the insulating material used to isolate the via contacts on the bottom surface (second dielectric layer).
8. The method of claim 1 wherein the package substrate comprises a printed circuit board, metallic, ceramic, semiconductor or leadframe based substrate.
Building upon the semiconductor package method, the package substrate can be a printed circuit board, or made from metallic, ceramic, semiconductor, or leadframe-based materials.
9. The method of claim 1 wherein the first end of the wire bond is bonded to die pad of the die so as to form a ball bond while the second end of the wire bond is bonded to the contact pad so as to form a stitch bond.
Building upon the semiconductor package method, one end of the insulated wire is attached to the chip pad using a ball bond, while the other end is attached to the contact pad on the substrate using a stitch bond.
10. The method of claim 9 comprising providing protective layers to cover the ball bond and the stitch bond.
Building upon the method of using ball and stitch bonds, protective layers are added to cover both the ball bond on the chip and the stitch bond on the substrate.
11. The method of claim 1 wherein the first end of the wire bond comprises a ball which is electrically coupled to the contact pad and the second end of the wire bond is bonded to a stud bump which is over the die pad so as to form a stitch bond.
Building upon the semiconductor package method, one end of the insulated wire is a ball that connects to the contact pad on the substrate. The other end of the wire is attached to a small raised bump (stud bump) on the chip pad using a stitch bond.
12. The method of claim 11 comprising providing protective layers to cover the stud bump and the ball bond.
Building upon the method of using a ball bond to the contact pad and a stitch bond to a stud bump, protective layers are added to cover both the stud bump on the die and the ball bond on the contact pad.
13. The method of claim 1 comprising providing a surface mount device over the first surface of the package substrate and wherein the wire bond comprises a loop profile having a lateral curvature.
Building upon the semiconductor package method, a surface mount device is placed on the substrate's top surface and the insulated wires connecting the chip to the contact pads are curved sideways, not just up and down.
14. The method of claim 1 wherein the cap comprises a top portion and sidewalls, wherein the top portion and sidewalls of the cap are made of different materials.
Building upon the semiconductor package method, the cap has a top and side walls. These top and side wall components of the cap are constructed using different materials.
15. The method of claim 1 wherein: the cap comprises a top portion and sidewall; and the access port extends through inner and outer surfaces of the sidewall of the cap.
Building upon the semiconductor package method, the cap has a top and side walls. The opening in the package through which the insulated wires are exposed to the environment is located in the side wall of the cap, passing through its inner and outer surfaces.
16. The method of claim 15 comprising providing a sealing ring surrounding the sensing element and providing a lid over a top surface of the sealing ring.
Building upon the method of the access port extending through the sidewall of the cap, a sealing ring is placed around the sensing element on the die and a lid is placed on top of this sealing ring to protect the element.
17. The method of claim 1 wherein the access port passes through the first and second surfaces of the package substrate.
Building upon the semiconductor package method, the opening in the package that exposes the insulated wires to the environment goes all the way through the substrate, from the top surface to the bottom surface.
18. The method of claim 17 wherein: the die has a recess which extends from an inactive surface of the die; and the sensing element is disposed at the bottom of the recess.
Building upon the method of the access port passing through the substrate, the chip has a recessed area on its inactive (back) side, and the sensing element is located at the bottom of this recessed area.
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October 10, 2013
April 4, 2017
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