The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device, comprising: a first fin having a rectangular parallelepiped shape extending in a first direction; a second fin having a rectangular parallelepiped shape arranged being spaced from and parallel to the first fin; a gate electrode arranged over the first and second fins via a gate insulating film and extending in a second direction intersecting the first direction; a first drain diffusion layer formed in the first fin located on one side of the gate electrode; a first source diffusion layer formed in the first fin located on the other side of the gate electrode; a second drain diffusion layer formed in the second fin located on one side of the gate electrode; a second source diffusion layer formed in the second fin located on the other side of the gate electrode; a drain region arranged over the first and second drain diffusion layers and extending in the second direction; a source region arranged over the first and second source diffusion layers and extending in the second direction; a first drain plug formed over the drain region; and a plurality of source plugs, including a first source plug and a second source plug, formed over the source region and arranged being spaced from each other, wherein the first source plug and the second source plug are arranged so that their positions in the second direction overlap with the first fin and the second fin, respectively, wherein the first source plug and the second source plug are arranged so that their positions are adjacent in the second direction, and wherein, so as to correspond to a region between the first source plug and the second source plug, the first drain plug is arranged in a displaced manner so that its position in the second direction does not overlap with any of the plurality of source plugs, including the first source plug and the second source plug.
A semiconductor device has two parallel, rectangular fins. A gate electrode sits on top of these fins, separated by a gate insulating film, running perpendicular to the fins. On one side of the gate is a drain region, connected to the first and second fins via drain diffusion layers. On the other side is a source region, connected to the first and second fins via source diffusion layers. A single drain plug connects to the drain region. Two source plugs connect to the source region, spaced apart from each other, each overlapping one fin. The drain plug is positioned so it doesn't overlap the source plugs; it's placed in the gap between them. This design reduces gate-drain capacitance compared to gate-source capacitance, minimizing signal delay.
2. The semiconductor device according to claim 1 , wherein the first source plug is formed over a region in which the first fin and the source region cross over, and wherein the second source plug is formed over a region in which the second fin and the source region cross over.
This semiconductor device is based on the device having two parallel, rectangular fins. A gate electrode sits on top of these fins, separated by a gate insulating film, running perpendicular to the fins. On one side of the gate is a drain region, connected to the first and second fins via drain diffusion layers. On the other side is a source region, connected to the first and second fins via source diffusion layers. A single drain plug connects to the drain region. Two source plugs connect to the source region, spaced apart from each other, each overlapping one fin. The drain plug is positioned so it doesn't overlap the source plugs; it's placed in the gap between them. The first source plug makes contact where the first fin and the source region overlap, and the second source plug makes contact where the second fin and the source region overlap.
3. The semiconductor device according to claim 1 , comprising: a third fin having a rectangular parallelepiped shape arranged being spaced from and parallel to the second fin; a fourth fin having a rectangular parallelepiped shape arranged being spaced from and parallel to the third fin; a third drain diffusion layer formed in the third fin located on one side of the gate electrode; a third source diffusion layer formed in the third fin located on the other side of the gate electrode; a fourth drain diffusion layer formed in the fourth fin located on one side of the gate electrode; and a fourth source diffusion layer formed in the fourth fin located on the other side of the gate electrode, wherein the gate electrode is arranged over the first, second, third, and fourth fins via the gate insulating film, wherein the drain region is arranged over the first, second, third, and fourth drain diffusion layers, wherein the source region is arranged over the first, second, third, and fourth source diffusion layers, wherein the first drain plug, a second drain plug, and a third drain plug are arranged over the drain region, wherein the first, the second, a third, and a fourth source plugs are arranged over the source region, wherein, so as to correspond to a region between the second and third source plugs, the second drain plug is arranged in a displaced manner so that its position in the second direction does not overlap with the second source plug or the third source plug, and wherein, so as to correspond to a region between the third and fourth source plugs, the third drain plug is arranged in a displaced manner so that its position in the second direction does not overlap with the third source plug or the fourth source plug.
A semiconductor device contains four parallel, rectangular fins. A gate electrode sits atop all four fins, separated by a gate insulating film, and runs perpendicular to them. Drain and source regions are formed on either side of the gate electrode, with respective drain and source diffusion layers connecting each fin to its respective region. Three drain plugs are positioned above the drain region. Four source plugs are positioned above the source region. The second drain plug is displaced so that it does not overlap the second or third source plugs. The third drain plug is displaced so that it does not overlap the third or fourth source plugs.
4. The semiconductor device according to claim 3 , wherein the first source plug is formed over a region in which the first fin and the source region cross over, wherein the second source plug is formed over a region in which the second fin and the source region cross over, wherein the third source plug is formed over a region in which the third fin and the source region cross over, and wherein the fourth source plug is formed over a region in which the fourth fin and the source region cross over.
This semiconductor device is based on the device containing four parallel, rectangular fins. A gate electrode sits atop all four fins, separated by a gate insulating film, and runs perpendicular to them. Drain and source regions are formed on either side of the gate electrode, with respective drain and source diffusion layers connecting each fin to its respective region. Three drain plugs are positioned above the drain region. Four source plugs are positioned above the source region. The second drain plug is displaced so that it does not overlap the second or third source plugs. The third drain plug is displaced so that it does not overlap the third or fourth source plugs. The first source plug makes contact where the first fin and the source region overlap, the second where the second fin and source region overlap, the third where the third fin and source region overlap, and the fourth where the fourth fin and source region overlap.
5. The semiconductor device according to claim 1 , comprising: a third fin having a rectangular parallelepiped shape arranged being spaced from and parallel to the second fin; a fourth fin having a rectangular parallelepiped shape arranged being spaced from and parallel to the third fin; a third drain diffusion layer formed in the third fin located on one side of the gate electrode; a third source diffusion layer formed in the third fin located on the other side of the gate electrode; a fourth drain diffusion layer formed in the fourth fin located on one side of the gate electrode; and a fourth source diffusion layer formed in the fourth fin located on the other side of the gate electrode, wherein the gate electrode is arranged over the first, second, third, and fourth fins via the gate insulating film, wherein the drain region includes a first drain part and a second drain part, wherein the first drain part is arranged over the first and second drain diffusion layers, wherein the second drain part is arranged over the third and fourth drain diffusion layers, wherein the source region is arranged over the first, second, third, and fourth diffusion layers, wherein the first drain plug is arranged over the first drain part, wherein a second drain plug is arranged over the second drain part, wherein the first, the second, a third, and a fourth source plugs are arranged over the source region, wherein, so as to correspond to a region between the third source plug and the fourth source plug, the second drain plug is arranged in a displaced manner so that its position in the second direction does not overlap with the third source plug or the fourth source plug, and wherein the second drain part is spaced from the first drain part.
A semiconductor device has four parallel, rectangular fins. A gate electrode sits atop all four fins, separated by a gate insulating film, and runs perpendicular to them. Drain and source regions are formed on either side of the gate electrode. The drain region has two distinct parts: one connected to the first and second fins, and the other to the third and fourth fins via drain diffusion layers. A single source region is formed over all the first, second, third and fourth diffusion layers. Two drain plugs connect to each drain part respectively. Four source plugs are positioned above the source region. The second drain plug, connected to the drain part over the third and fourth fins, is placed so it does not overlap the third or fourth source plugs. The drain parts are separated from each other.
6. The semiconductor device according to claim 5 , wherein the first source plug is formed over a region in which the first fin and the source region cross over, wherein the second source plug is formed over a region in which the second fin and the source region cross over, wherein the third source plug is formed over a region in which the third fin and the source region cross over, and wherein the fourth source plug is formed over a region in which the fourth fin and the source region cross over.
This semiconductor device is based on the device having four parallel, rectangular fins. A gate electrode sits atop all four fins, separated by a gate insulating film, and runs perpendicular to them. Drain and source regions are formed on either side of the gate electrode. The drain region has two distinct parts: one connected to the first and second fins, and the other to the third and fourth fins via drain diffusion layers. A single source region is formed over all the first, second, third and fourth diffusion layers. Two drain plugs connect to each drain part respectively. Four source plugs are positioned above the source region. The second drain plug, connected to the drain part over the third and fourth fins, is placed so it does not overlap the third or fourth source plugs. The drain parts are separated from each other. The first source plug makes contact where the first fin and the source region overlap, the second where the second fin and source region overlap, the third where the third fin and source region overlap, and the fourth where the fourth fin and source region overlap.
7. The semiconductor device according to claim 1 , wherein a number of drain plugs included in the semiconductor device is set to be smaller than a number of the plurality of source plugs.
This semiconductor device is based on the device having two parallel, rectangular fins. A gate electrode sits on top of these fins, separated by a gate insulating film, running perpendicular to the fins. On one side of the gate is a drain region, connected to the first and second fins via drain diffusion layers. On the other side is a source region, connected to the first and second fins via source diffusion layers. A single drain plug connects to the drain region. Two source plugs connect to the source region, spaced apart from each other, each overlapping one fin. The drain plug is positioned so it doesn't overlap the source plugs; it's placed in the gap between them. The number of drain plugs used in this design is less than the number of source plugs.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 10, 2015
April 11, 2017
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