To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.
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1. A semiconductor device comprising: a semiconductor chip including a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
A semiconductor device includes a semiconductor chip with a main surface and multiple electrode pads on that surface. These electrode pads connect to external leads via wires. Among the electrode pads are several "first" pads that receive multiple bits of data simultaneously (in parallel). Two of these "first" pads are designated as "second" and "third" electrode pads. Crucially, a "fourth" electrode pad, which is *not* one of the "first" parallel-bit pads, sits physically between the "second" and "third" pads.
2. The semiconductor device according to claim 1 , wherein the second, third and fourth electrode pads are arranged along one of the plurality of sides.
In the semiconductor device described above, the "second," "third," and "fourth" electrode pads are positioned along one of the edges (sides) of the semiconductor chip's main surface. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
3. The semiconductor device according to claim 2 , wherein the semiconductor chip is equipped with an internal circuit which generates the plurality of bits, and wherein the plurality of bits are supplied from the internal circuit to the second and third electrode pads in parallel.
In the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip, the semiconductor chip contains an internal circuit. This internal circuit *generates* the multiple bits of data that are fed in parallel to the "second" and "third" electrode pads. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
4. The semiconductor device according to claim 2 , wherein the plurality of bits are supplied from the outside of the semiconductor device to the second and third electrode pads in parallel.
Instead of generating the parallel bits internally, in the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip, the multiple bits are supplied *from outside* the semiconductor device to the "second" and "third" electrode pads simultaneously (in parallel). The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
5. The semiconductor device according to claim 2 , wherein the fourth electrode pad is one of a plurality of fourth electrode pads, and wherein the fourth electrode pads are supplied with a plurality of bits in parallel.
In the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip, the "fourth" electrode pad is actually *one of several* "fourth" electrode pads. These multiple "fourth" electrode pads themselves receive multiple bits of data simultaneously (in parallel). The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
6. The semiconductor device according to claim 2 , wherein the fourth electrode pads includes an electrode pad supplied with a power supply voltage.
In the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip, at least one of the "fourth" electrode pads is specifically connected to a power supply voltage. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
7. The semiconductor device according to claim 2 , wherein the first electrode pads are arranged along the one side are all coupled to the leads by a plurality of wires.
In the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip, *all* of the "first" electrode pads located along that edge are connected to external leads via wires. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
8. The semiconductor device according to claim 6 , wherein the second and third electrode pads arranged along the one side are respectively coupled to the leads by a plurality of wires, and wherein the fourth electrode pads arranged along the one side have electrode pads coupled to the leads by a plurality of wires, and electrode pads which are not coupled to the leads.
Considering the semiconductor device where the "second," "third," and "fourth" electrode pads are positioned along one edge of the chip and one or more of the "fourth" pads is connected to a power supply voltage, the "second" and "third" electrode pads on that edge are always connected to external leads with wires. However, the "fourth" electrode pads on that edge *may or may not* be connected to leads. Some "fourth" pads are connected, and some are not. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
9. The semiconductor device according to claim 3 , wherein the internal circuit includes a plurality of registers corresponding to the plurality of bits, and wherein the registers are coupled to the second and third electrode pads.
In the semiconductor device including an internal circuit generating parallel bits for the second and third pads (and where the second, third, and fourth pads are positioned along an edge of the chip), the internal circuit contains multiple registers. There is one register for each of the parallel bits. These registers are directly connected to the "second" and "third" electrode pads to output the data. The semiconductor chip has a main surface surrounded by a plurality of sides, and a plurality of electrode pads arranged over the main surface; and a plurality of leads coupled to the electrode pads by way of a plurality of wires respectively, wherein the plurality of electrode pads include a plurality of first electrode pads supplied with a plurality of bits in parallel, wherein the plurality of first electrode pads include second and third electrode pads, and wherein a fourth electrode pad different from the plurality of first electrode pads is arranged between the second and third electrode pads.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 12, 2015
April 18, 2017
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