Disclosed are a data training device and a semiconductor device. The data training device includes a write controller configured to align write data, a read controller configured to latch data applied from the write controller and sequentially output the latched data, and an offset compensator configured to adjust a current flowing through a power supply voltage application terminal and a ground voltage application terminal in correspondence to a write signal and a read signal, thereby compensating for an offset in the write controller and the read controller.
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1. A data training device comprising: a write controller configured to align write data; a read controller configured to latch data applied from the write controller and sequentially output the latched data; and an offset compensator configured to adjust a current flowing through a power supply voltage application terminal and a ground voltage application terminal in correspondence to a write signal and a read signal, thereby compensating for an offset in the write controller and the read controller, wherein the write controller, the read controller and the offset compensator receive voltages through the power supply voltage application terminal and the ground voltage application terminal, respectively.
A data training device corrects for signal offsets during data writing and reading. It includes a write controller that aligns incoming data for writing, a read controller that latches the written data and outputs it sequentially, and an offset compensator. The offset compensator adjusts the current flowing through the power supply and ground terminals based on the write and read signals to counteract offsets in the write and read controllers. The write controller, read controller, and offset compensator all receive power through the same power supply and ground terminals.
2. The data training device of claim 1 , further comprising: a data input circuit configured to buffer data applied from an exterior and output the buffered data to the write controller.
The data training device, which includes a write controller for aligning data, a read controller for latching and outputting data, and an offset compensator for current adjustment, also has a data input circuit. This input circuit buffers data coming from an external source and then sends the buffered data to the write controller for processing.
3. The data training device of claim 1 , further comprising: a data output circuit configured to buffer read data applied from the read controller and output the buffered data to an exterior.
The data training device, which includes a write controller for aligning data, a read controller for latching and outputting data, and an offset compensator for current adjustment, also has a data output circuit. This output circuit buffers the read data that's coming from the read controller and then sends that buffered data to an external destination.
4. The data training device of claim 1 , further comprising: a decoder configured to decode a command signal and output the write signal and the read signal to the offset compensator.
The data training device, which includes a write controller for aligning data, a read controller for latching and outputting data, and an offset compensator for current adjustment, also has a decoder. This decoder takes a command signal, interprets it, and outputs the write signal and the read signal to the offset compensator, controlling when writing and reading occur.
5. The data training device of claim 4 , wherein the decoder decodes a MPC (Multi-Purpose Command) signal, thereby generating the write signal and the read signal.
The data training device includes a decoder which receives a command signal, and outputs write and read signals to the offset compensator, in addition to a write controller for aligning data, a read controller for latching and outputting data, and an offset compensator for current adjustment. Specifically, the decoder interprets a Multi-Purpose Command (MPC) signal to generate the write and read signals.
6. The data training device of claim 1 , wherein the read controller includes a plurality of FIFO (First Input First Output) latches.
The data training device includes a write controller for aligning data, a read controller for latching and outputting data, and an offset compensator for current adjustment. The read controller uses multiple FIFO (First-In, First-Out) latches to temporarily store the data before it is outputted sequentially.
7. The data training device of claim 1 , wherein the offset compensator comprises: an enable signal generator configured to control and output pulse widths of a write/read enable signal and a read enable signal in correspondence to the write signal and the read signal; and a current controller configured to control a current flowing through the write controller and the read controller in correspondence to the write/read enable signal and the read enable signal.
The data training device contains an offset compensator comprising an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The enable signal generator controls the pulse widths of write/read enable signals and a read enable signal based on the write and read signals. The current controller adjusts the current flowing through the write and read controllers based on these enable signals.
8. The data training device of claim 7 , wherein the enable signal generator activates the write/read enable signal when one or more of the write signal and the read signal are enabled.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The enable signal generator activates the combined write/read enable signal whenever either the write signal or the read signal is active.
9. The data training device of claim 7 , wherein the enable signal generator activates the read enable signal when the read signal is enabled.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The enable signal generator activates the read enable signal specifically when the read signal is active.
10. The data training device of claim 7 , wherein the current controller controls the current based on an amount of a current consumed when a cell array operates.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller adjusts the current flowing through the write and read controllers, taking into account the current that is consumed when the memory cell array is operating.
11. The data training device of claim 7 , wherein the current controller adjusts a current flowing through the write controller and the read controller during a period in which the write/read enable signal and the read enable signal are activated.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller adjusts the current flowing through the write and read controllers only during the periods when the write/read enable signal and the read enable signal are active.
12. The data training device of claim 7 , wherein the current controller generates current values different from each other in a write operation and a read operation, thereby compensating for an offset voltage.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller generates different current values for the write and read operations, allowing it to compensate for any offset voltage between the two operations.
13. The data training device of claim 7 , wherein the current controller includes a plurality of switching elements and adjusts a current value through adjustment of a number of switching elements to be turned on according to activation or deactivation of the write/read enable signal and the read enable signal.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller uses multiple switching elements, and the current is adjusted by changing the number of switching elements that are turned on or off based on the activation of the write/read enable signal and the read enable signal.
14. The data training device of claim 7 , wherein the current controller includes a plurality of switching elements which are coupled in parallel with one another between the power supply voltage application terminal and the ground voltage application terminal and receive the write/read enable signal and the read enable signal through gate terminals thereof.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller includes multiple switching elements connected in parallel between the power supply and ground. The write/read enable signal and read enable signal control these switching elements through their gate terminals.
15. The data training device of claim 14 , wherein, among the plurality of switching elements, some switching elements receive the write/read enable signal through gate terminals thereof, and other switching elements receive the read enable signal through gate terminals thereof.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller has multiple parallel switching elements between the power supply and ground. Some of these switches are controlled by the write/read enable signal, while others are controlled by the read enable signal, providing independent control for write and read current adjustment.
16. The data training device of claim 14 , wherein, in the current controller, some switching elements are turned on in a write operation and all the switching elements are turned on in a read operation.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The current controller uses switching elements. Some of these switches are turned on during the write operation, and all of them are turned on during the read operation. This enables different current levels for writing and reading.
17. The data training device of claim 7 , wherein the write/read enable signal is activated during a write recovery time (tWR) after all data is written in a cell in a write operation.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The write/read enable signal is activated during the write recovery time (tWR) after all the data has been written to the memory cell in the write operation.
18. The data training device of claim 7 , wherein the read enable signal is activated at a time at which the read signal is enabled and is disabled during a precharge period before first data is outputted.
The data training device includes an offset compensator that contains an enable signal generator and a current controller, in addition to a write controller for aligning data and a read controller for latching and outputting data. The read enable signal is activated when the read signal is enabled, but is disabled during the precharge period before the first data is output.
19. A semiconductor device comprising a data training device configured to align and latch write data, and adjust a current flowing through a power supply voltage application terminal and a ground voltage application terminal in correspondence to a write signal and a read signal, thereby compensating for an offset in an input/output terminal of write data and read data wherein the data training device comprises: a write controller configured to align the write data; a read controller configured to latch data applied from the write controller and sequentially output the latched data; and an offset compensator configured to adjust a current of the input/output terminal in correspondence to the write signal and the read signal, wherein the write controller, the read controller and the offset compensator receive voltages through the power supply voltage application terminal and the ground voltage application terminal, respectively.
A semiconductor device incorporates a data training device to align and latch write data, and adjust current to compensate for offsets in the data input/output. The data training device includes a write controller that aligns the write data, a read controller that latches the data from the write controller and outputs it sequentially, and an offset compensator that adjusts the current of the input/output terminal in response to write and read signals. These components receive voltages via the power supply and ground terminals. This arrangement corrects for signal offsets at the input/output terminal.
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June 9, 2016
May 9, 2017
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