Patentable/Patents/US-9646851
US-9646851

Embedded semiconductive chips in reconstituted wafers, and systems containing same

PublishedMay 9, 2017
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Patent Claims
14 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A process of forming a reconstituted wafer, comprising: disposing a plurality of semiconductive dice above a backing plate, wherein the plurality of semiconductive dice includes a first die and wherein the first die includes at least one terminal on an active surface of the first die; embedding the plurality of semiconductive dice in a mass, wherein the mass obscures the at least one terminal of the first die, and wherein portions of the mass extend over and contact portions of the first die active surface; and removing a portion of the mass to expose the at least one terminal of the first die and to form a first surface; and removing the backing plate.

Plain English Translation

A method for creating a reconstituted wafer involves positioning multiple semiconductor dice (chips) above a temporary backing plate. At least one of these chips has electrical contacts (terminals) on its active surface. The chips are then embedded in a rigid material, like epoxy, that covers the terminals. A portion of this embedding material is then removed, typically by grinding or polishing, to expose the terminals and create a flat, uniform top surface. Finally, the backing plate is removed, resulting in a reconstituted wafer where the chips are embedded in a rigid matrix with their terminals accessible.

Claim 2

Original Legal Text

2. The process of claim 1 , further comprising disposing an adhesive on the backing plate prior to disposing the plurality of semiconductive dice above the backing plate, and further comprising removing the adhesive after removing the portion of the mass.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, further involves adding an adhesive layer between the backing plate and the chips before placing the chips. After the mass is removed to expose the terminals, this adhesive layer is also removed, separating the reconstituted wafer from the backing plate completely. This ensures the chips are securely held during the initial embedding process.

Claim 3

Original Legal Text

3. The process of claim 1 , wherein removing a portion of the mass comprises grinding the mass.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes a specific method for removing the mass: grinding. This involves using abrasive tools to mechanically remove the embedding material until the chip terminals are exposed and the top surface is planarized, creating a uniform surface suitable for further processing or connections.

Claim 4

Original Legal Text

4. The process of claim 1 , wherein removing a portion of the mass comprises polishing the mass.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes a specific method for removing the mass: polishing. This utilizes fine abrasives and a polishing pad to achieve a smooth, flat surface by removing the embedding material and exposing the terminals. Polishing is often used after grinding to further refine the surface quality.

Claim 5

Original Legal Text

5. The process of claim 1 , wherein removing a portion of the mass comprises grinding followed by polishing.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes a specific method for removing the mass: a combination of grinding followed by polishing. This utilizes grinding for efficient material removal and planarization, followed by polishing to achieve a smoother surface finish and precise terminal exposure.

Claim 6

Original Legal Text

6. The process of claim 1 , further including cutting at least one of the plurality of semiconductive dice from the plurality of semiconductive dice after removing the backing plate.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, also includes singulating individual chips (or groups of chips) after the backing plate has been removed. This involves cutting through the embedding material to separate individual dice from the reconstituted wafer, allowing them to be used in separate applications.

Claim 7

Original Legal Text

7. The process of claim 1 , further including forming metallizations above the first surface to connect to the at least one terminal of the first die.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes creating electrical connections to the exposed terminals. Specifically, this involves depositing conductive materials (metallizations) on the newly formed flat surface to connect to the terminals of the embedded chips, enabling electrical communication with the chips.

Claim 8

Original Legal Text

8. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes forming a bumpless build-up layer (BBUL) on the exposed surface. A BBUL is a layer used to create fine-pitch interconnections without solder bumps, offering a method for advanced packaging and direct chip-to-chip or chip-to-board connections.

Claim 9

Original Legal Text

9. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface prior to removing the backing plate.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes forming a bumpless build-up layer (BBUL) on the exposed surface *before* the backing plate is removed. This BBUL acts as an intermediate layer for creating connections and can be built up before the reconstituted wafer is fully separated.

Claim 10

Original Legal Text

10. The process of claim 9 , further including cutting at least one of the plurality of semiconductive dice from the plurality of semiconductive dice after removing the backing plate.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, and also includes forming a bumpless build-up layer (BBUL) above the exposed surface prior to removing the backing plate, further includes cutting individual chips (or groups of chips) after the backing plate has been removed. This involves separating individual dice from the reconstituted wafer for integration into various applications after the BBUL is formed.

Claim 11

Original Legal Text

11. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface; and coupling a device to the BBUL and to at least one of the plurality of semiconductive dice, wherein the BBUL is between the device and the plurality of semiconductive dice.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes forming a bumpless build-up layer (BBUL) on the exposed surface. Additionally, this process involves connecting a device to both the BBUL and at least one of the embedded semiconductor chips. The BBUL serves as an intermediary connection layer between the device and the chip, enabling signal routing and electrical connectivity.

Claim 12

Original Legal Text

12. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface; and coupling a plurality of devices to the BBUL and to at least one of the plurality semiconductive dice, wherein the BBUL is between the plurality of devices and the plurality of semiconductive die, and wherein at least one device of the plurality of devices is a passive device.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, includes forming a bumpless build-up layer (BBUL) on the exposed surface. This process also involves connecting multiple devices to the BBUL and to at least one of the semiconductor chips. The BBUL acts as an intermediary layer, and at least one of the connected devices is a passive component (e.g., resistor, capacitor, inductor), integrated directly onto the reconstituted wafer for improved circuit performance.

Claim 13

Original Legal Text

13. The process of claim 1 , further wherein embedding the plurality of semiconductive dice in a mass comprises embedding the plurality of semiconductive dice in an epoxy.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, the chips are then embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, specifies the embedding material as an epoxy resin. The epoxy encapsulates the chips, providing structural support and electrical insulation, before being planarized to expose the chip terminals.

Claim 14

Original Legal Text

14. The process of claim 1 , further wherein embedding the plurality of semiconductive dice in a mass comprises embedding the plurality of semiconductive dice in a material selected from the group consisting of silicones, polyimides, epoxy-acrylates, and liquid crystal polymers.

Plain English Translation

The process of forming a reconstituted wafer, where multiple semiconductor chips are placed on a backing plate, embedded in a mass obscuring their terminals, and then the mass is partially removed to expose the terminals, specifies that the embedding material is selected from a group of materials including silicones, polyimides, epoxy-acrylates, and liquid crystal polymers. These materials are used to encapsulate the chips, and each material offers different thermal, mechanical, and electrical properties depending on the application requirements.

Classification Codes (CPC)

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Patent Metadata

Filing Date

March 15, 2016

Publication Date

May 9, 2017

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