Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.
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1. A semiconductor device, comprising: a single base substrate, in a planar or non-planar configuration, comprising one or more first gate stacks and one or more second gate stacks; the one or more first gate stack comprising: a first silicon material layer disposed directly on a first semiconductor material substrate; a first dielectric material layer disposed on the first silicon material layer; and a masking layer disposed on the first dielectric material layer; the one or more second gate stacks comprising: a second silicon material layer disposed directly on a second semiconductor material substrate; a second dielectric material layer disposed on the second silicon material layer; and a catalytic material layer formed on top of the second dielectric material layer, such that no catalytic material layer is formed on top of the first dielectric material layer, wherein the catalytic material layer is selected from the group consisting of rhodium, ruthenium, and nickel; and source and drain regions adjacent to the one or more first and second gate stacks, wherein the hydrogen content of the first silicon material layer is different from the hydrogen content of the second silicon material layer; and wherein the one or more first gate stacks have a threshold voltage (Vt) different from the one or more second gate stacks.
A semiconductor device (like a transistor) has a base substrate (either flat or with fins) containing two types of gate stacks: "first" and "second". The "first" gate stack has a silicon layer directly on the semiconductor material, a dielectric layer (insulator) on that, and a masking layer on top. The "second" gate stack has a silicon layer directly on the semiconductor material, a dielectric layer on that, and a catalytic material layer (rhodium, ruthenium, or nickel) on top. Critically, the first gate stack does NOT have this catalytic layer. Source and drain regions are next to both gate stacks. The key is the silicon layers: the "first" silicon layer has a DIFFERENT hydrogen content than the "second" silicon layer, resulting in DIFFERENT threshold voltages (Vt) for the two gate stacks.
2. The device of claim 1 , wherein the first and second semiconductor material substrates and the base substrate include silicon (Si), germanium (Ge), silicon-germanium (SiGe), SiC, III-V compounds, or any combination thereof.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the base substrate, the first semiconductor substrate, and the second semiconductor substrate can be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), SiC, III-V compounds, or any combination of these materials. This means the foundational material upon which the device is built (substrate and semiconductor beneath the silicon layers) isn't limited to just silicon; other materials are possible, allowing for different electronic properties.
3. The device of claim 1 , wherein the first silicon material layer and the second silicon material layer independently include amorphous silicon (aSi), hydrogenated amorphous silicon (aSi:H), polysilicon (polySi), hydrogenated polysilicon (polySi:H), nanocrystalline silicon (nc-Si), or hydrogenated nanocrystalline silicon (nc-Si:H).
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the silicon material used for the first and second silicon layers can be independently selected from amorphous silicon (aSi), hydrogenated amorphous silicon (aSi:H), polysilicon (polySi), hydrogenated polysilicon (polySi:H), nanocrystalline silicon (nc-Si), or hydrogenated nanocrystalline silicon (nc-Si:H). The layers don't have to be the same type of silicon; one could be amorphous and the other polysilicon, for example, to further tailor device characteristics.
4. The device of claim 1 , wherein each of the first silicon material layer and the second silicon material layer has a thickness of less than 50 Angstroms.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where both the first and second silicon material layers are very thin, specifically less than 50 Angstroms thick. This thinness is important for controlling the transistor's behavior at a very small scale.
5. The device of claim 1 , wherein the first dielectric material layer and the second dielectric material layer independently include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), boron nitride, high-k materials, or a combination thereof.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the dielectric layers in the first and second gate stacks can be independently chosen from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), boron nitride, high-k materials (materials with a high dielectric constant), or any combination of these. This allows flexibility in choosing the insulating material based on desired electrical properties and compatibility with other layers.
6. The device of claim 1 , wherein the first dielectric material layer and the second dielectric material layer independently include hafnium oxide (HfO), hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide (LaO), lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide (AlO), lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the dielectric layers in the first and second gate stacks can be independently chosen from a specific list of high-k materials, including hafnium oxide (HfO), hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide (LaO), lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide (AlO), lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. This provides a more detailed list of suitable high-k dielectric materials for the insulating layers.
7. The device of claim 1 , wherein the first and second semiconductor material substrates comprise InGaAs and the device is a n-channel device.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the semiconductor material beneath the first and second silicon layers is specifically InGaAs and the resulting transistor is an n-channel device. Specifying InGaAs as the semiconductor material implies certain performance characteristics suitable for n-channel transistors.
8. The device of claim 1 , wherein the first silicon material layer and the second silicon material layer originated from different types of silicon material.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the first and second silicon material layers were created using different silicon materials initially. For example, one layer may have been made from amorphous silicon and another from polysilicon to achieve the difference in hydrogen content and therefore threshold voltage.
9. The device of claim 1 , wherein the first silicon material layer and the second silicon material layer originated from the same type of silicon material.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the first and second silicon material layers were created from the SAME type of silicon material initially. This implies that the different hydrogen content is achieved through processing steps after deposition, rather than starting with different materials.
10. The device of claim 1 , wherein each of the first silicon material layer and the second silicon material layer has a thickness of 5 to 40 Angstroms.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the first and second silicon material layers have a thickness between 5 and 40 Angstroms. This narrows the thickness range down from the broader "<50 Angstroms" specified previously.
11. The device of claim 1 , wherein each of the first silicon material layer and the second silicon material layer has a thickness of 20 to 30 Angstroms.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the first and second silicon material layers have a thickness between 20 and 30 Angstroms. This further refines the optimal thickness range for the silicon layers.
12. The device of claim 1 , wherein the single base substrate in the non-planar configuration comprises a first fin and a second fin.
The semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where the single base substrate is non-planar and includes a first fin and a second fin. The fins are vertical structures around which the gate stacks are formed, creating a FinFET transistor.
13. The device of claim 12 , wherein the first silicon material layer is disposed around the first fin.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer (of the first gate stack) is disposed *around* the first fin. This means the silicon layer conforms to the shape of the fin.
14. The device of claim 13 , wherein the second silicon material layer is disposed around the second fin.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, and the second silicon material layer (of the second gate stack) is disposed *around* the second fin. Thus, each fin has its own gate stack structure.
15. The device of claim 14 , wherein the first fin and the second fin extend vertically.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, the second silicon material layer is disposed around the second fin, and the first and second fins extend vertically. This clarifies the orientation of the fins relative to the substrate.
16. The device of claim 14 , wherein the single base substrate is the same material as the first fin and the second fin.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, the second silicon material layer is disposed around the second fin, the single base substrate and the first/second fins are made of the same material. This simplifies manufacturing since it avoids material interface issues.
17. The device of claim 14 , wherein an interlayer is disposed between the single base substrate and the first and second fins.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, the second silicon material layer is disposed around the second fin, and an interlayer is disposed between the single base substrate and the first and second fins. This adds a layer between the fins and the underlying substrate.
18. The device of claim 17 , wherein the interlayer isolates the first and second fins from the single base substrate.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, the second silicon material layer is disposed around the second fin, an interlayer is disposed between the single base substrate and the first and second fins, and this interlayer *isolates* the first and second fins from the single base substrate. This electrical isolation can improve device performance.
19. The device of claim 18 , wherein the interlayer is an insulating material.
In the FinFET semiconductor device with two different gate stacks (first and second) having different hydrogen content in the silicon layers to create different threshold voltages (Vt), where there is a first fin and a second fin, the first silicon material layer is disposed around the first fin, the second silicon material layer is disposed around the second fin, an interlayer is disposed between the single base substrate and the first and second fins, the interlayer isolates the first and second fins from the single base substrate, and the interlayer is made of an insulating material. This specifies the material property needed for isolation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 7, 2016
May 9, 2017
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