The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control gate separated from a floating gate by a control gate dielectric. An erase gate disposed on a first side of the gate stack. A word line is disposed on a second side of the gate stack that is opposite the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. The shape of the word line optimizes the contact resistance of the word line and allows for an overlying cap spacer formed on the word line to be well defined, which can provide more reliable read/write operations and/or better performance.
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1. A flash memory device, comprising: a gate stack comprising a control gate separated from a floating gate by a control gate dielectric; an erase gate disposed on a first side of the gate stack; and a word line disposed on a second side of the gate stack that is opposite the first side, wherein the word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack; wherein the word line comprises a ledge at the outer side of the word line with a planar upper surface, and a tilted portion at the inner side of the word line.
A flash memory device includes a gate stack (control gate, floating gate, and dielectric between them), an erase gate on one side of the gate stack, and a word line on the opposite side. The word line's height increases from its outer edge (away from the gate stack) to its inner edge (closer to the gate stack). The word line also has a flat ledge on its outer edge and a sloped or tilted section on its inner edge. This word line shape improves contact resistance and allows for a well-defined cap spacer to be formed on top, improving read/write operations.
2. The flash memory device of claim 1 , wherein a slope of a top surface of the tilted portion of the word line decreases from the outer side to the inner side of the tilted portion of the word line.
In the flash memory device with a word line having a flat ledge and tilted portion (as described in Claim 1), the slope of the top surface of the tilted portion of the word line gradually becomes less steep from the outer edge of the word line towards the inner edge (closer to the gate stack). This varying slope helps to further optimize the electric field distribution and improve device performance.
3. The flash memory device of claim 1 , wherein the tilted portion of the word line comprises an upper surface having a slope that decreases as a distance from the gate stack decreases.
In the flash memory device with a word line having a flat ledge and tilted portion (as described in Claim 1), the tilted portion of the word line's upper surface has a slope that decreases as the distance from the gate stack decreases. This means the slope is steeper farther from the gate stack and gentler nearer to it. This specific curvature enhances control over charge injection and extraction in the floating gate.
4. The flash memory device of claim 1 , wherein the erase gate has a planar upper surface.
In the flash memory device (as described in Claim 1), the erase gate has a flat upper surface. This planar surface simplifies manufacturing and provides a uniform electric field for the erase operation.
5. The flash memory device of claim 1 , further comprising: a word line cap spacer disposed on the word line and an erase gate cap spacer disposed on the erase gate; and a dielectric segment comprising a different material than the word line cap spacer, which is disposed at an upper outer edge of the word line cap spacer.
The flash memory device (as described in Claim 1) also includes a word line cap spacer on top of the word line, and an erase gate cap spacer on top of the erase gate. A small piece of dielectric material, different from the word line cap spacer, is placed on the upper outer edge of the word line cap spacer. This dielectric segment helps to further isolate the word line and prevent unwanted electrical interference and enhance device reliability.
6. The flash memory device of claim 1 , further comprising: a sidewall spacer disposed along an outer sidewall of the word line; an interlayer dielectric (ILD) layer arranged over the gate stack, the erase gate and the word line; silicide pads arranged over the word line and the erase gate; and conductive contacts extending through the ILD layer to the silicide pads.
The flash memory device (as described in Claim 1) also has a spacer on the outer side of the word line, an interlayer dielectric (ILD) layer covering the gate stack, erase gate, and word line. Silicide pads are on top of the word line and erase gate, and conductive contacts go through the ILD to connect to the silicide pads. This arrangement provides electrical connections to the word line and erase gate.
7. The flash memory device of claim 1 , wherein the gate stack further comprises a hard mask disposed over the control gate.
In the flash memory device (as described in Claim 1), the gate stack also has a hard mask on top of the control gate. This hard mask helps during the etching process to precisely define the shape of the gate stack components.
8. The flash memory device of claim 1 , wherein the floating gate has a floating gate ledge comprising a reduced height and surrounding a central region of the floating gate, and wherein the flash memory device further comprises a dielectric cap extending from the floating gate ledge over a top surface of the gate stack.
In the flash memory device (as described in Claim 1), the floating gate has a ledge with a reduced height surrounding its central region. A dielectric cap extends from this floating gate ledge over the top of the gate stack. This dielectric cap helps to isolate the floating gate and prevent charge leakage.
9. The flash memory device of claim 1 , further including: a second gate stack disposed on an opposite side of the erase gate as the gate stack, wherein the second gate stack comprises a second control gate arranged over a second floating gate; and a second word line disposed at a second side of the second gate stack as the erase gate, wherein the second word line has a height that monotonically increases from an outer side opposite to the second gate stack to an inner side closer to the second gate stack.
In addition to the features of Claim 1, the flash memory device also has a second gate stack, a second word line, and shares an erase gate. The second gate stack is located on the opposite side of the erase gate from the first gate stack and consists of a second control gate over a second floating gate. A second word line, located on the opposite side of this second gate stack from the erase gate, increases in height from its outer edge (away from the second gate stack) to its inner edge (closer to the second gate stack), mirroring the structure on the first side.
10. The flash memory device of claim 1 , wherein the erase gate and the word line share a crystalline structure.
In the flash memory device (as described in Claim 1), the erase gate and the word line are made from the same crystalline material. This simplifies manufacturing and can improve the reliability of the device by reducing stress at the interface between the erase gate and the word line.
11. An integrated circuit for a flash memory device, comprising: a common source/drain region shared by a pair of memory cells disposed in a substrate; a pair of gate stacks disposed at opposite sides of the common source/drain region over the substrate, wherein the pair of gate stacks respectively comprise a floating gate and a control gate arranged over the floating gate; a pair of word lines disposed at opposite sides of the gate stacks as the common source/drain region, wherein each of the pair of word lines has a height that monotonically increases from an outer side opposite to the gate stacks to an inner side closer to the gate stacks; a pair of sidewall spacers disposed along outer sidewalls of the word lines; an erase gate disposed over the common source/drain region between the gate stacks; and an erase gate cap spacer disposed over the erase gate, wherein an upper surface of the erase gate cap spacer is recessed.
An integrated circuit for a flash memory device has a common source/drain region shared by two memory cells. Two gate stacks, each with a floating gate and a control gate, are located on opposite sides of the common source/drain region. Two word lines, one for each gate stack, are on the opposite sides of the gate stacks from the common source/drain region. The height of each word line increases from its outer edge to its inner edge. Sidewall spacers are on the outer sides of the word lines. An erase gate is above the common source/drain region between the gate stacks, and an erase gate cap spacer is on top of the erase gate, where the upper surface of the erase gate cap spacer is recessed.
12. The integrated circuit of claim 11 , wherein each of the word lines comprises a ledge portion abutting the corresponding sidewall spacer, the ledge portion has a reduced height relative to a top surface of the word lines.
In the integrated circuit for a flash memory device with word lines of varying height (as described in Claim 11), each word line includes a flat ledge portion abutting the corresponding sidewall spacer. This ledge portion has a reduced height compared to the top surface of the rest of the word line. This configuration allows for more precise control of the electric field and reduces the risk of short circuits.
13. The integrated circuit of claim 12 , wherein each of the word lines comprises a tilted portion connecting to the ledge portion, wherein a slope of the top surface of the tilted portion of the word lines decreases from the outer side to the inner side of the tilted portion of the word lines.
In the integrated circuit described in Claim 12, where each word line has a ledge portion and a sidewall spacer, each word line also comprises a tilted portion connecting to the ledge portion. The slope of the top surface of this tilted portion gradually decreases from the outer side towards the inner side of the tilted portion. This specific contouring of the word line helps to optimize the device's performance.
14. The integrated circuit of claim 11 , further comprising: word line cap spacers disposed over the word lines and abutting upper portions of the sidewall spacers.
The integrated circuit for a flash memory device (as described in Claim 11) also includes word line cap spacers on top of the word lines, which abut the upper portions of the sidewall spacers. These cap spacers help to further insulate the word lines and prevent unwanted electrical interference.
15. A flash memory device, comprising: a gate stack arranged over a substrate and comprising a control gate separated from a floating gate by a control gate dielectric; a word line disposed on one side of the gate stack wherein the word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack; a word line cap spacer disposed on the word line, including a ledge locating at an upper outer edge of the word line cap spacer; and a dielectric segment comprising a different material than the word line cap spacer, which is disposed on the ledge of the word line cap spacer and has an outer sidewall vertically aligned with outer sidewalls of the word line and the word line cap spacer.
A flash memory device has a gate stack (control gate, floating gate, and dielectric) over a substrate. A word line is on one side of the gate stack and increases in height from its outer edge (away from the gate stack) to its inner edge (closer to the gate stack). A word line cap spacer is on top of the word line, including a ledge at its upper outer edge. A dielectric segment, different from the cap spacer, is on this ledge, and its outer side is vertically aligned with the outer sides of the word line and its cap spacer.
16. The flash memory device of claim 15 , wherein the word line cap spacer has a concave upper surface, such that a height of the word line cap spacer from the concave upper surface to a surface of the substrate monotonically decreases from a peripheral region to a middle region.
In the flash memory device with the dielectric segment on the word line cap spacer ledge (as described in Claim 15), the word line cap spacer has a concave upper surface, meaning its height from the surface of the substrate decreases from the edge regions towards the center. This concave shape helps to improve the electric field distribution and device performance.
17. The flash memory device of claim 15 , wherein the dielectric segment comprised nitride and the word line cap spacer comprises oxide.
In the flash memory device with the dielectric segment on the word line cap spacer ledge (as described in Claim 15), the dielectric segment is made of nitride, while the word line cap spacer is made of oxide. These different materials have different electrical properties that improve device performance and reliability.
18. The flash memory device of claim 15 , further comprising: an erase gate disposed on a side of the gate stack opposite to the word line; wherein the erase gate comprises a planar upper surface.
The flash memory device (as described in Claim 15) also includes an erase gate located on the opposite side of the gate stack from the word line. This erase gate has a planar upper surface.
19. The flash memory device of claim 18 , further comprising: an erase gate cap spacer disposed on the erase gate; wherein the erase gate cap spacer has a concave upper surface such that a height of the erase gate cap spacer from the concave upper surface to a surface of the substrate monotonically decreases from a peripheral region to a middle region.
In the flash memory device (as described in Claim 18), an erase gate cap spacer is disposed on the erase gate. The erase gate cap spacer has a concave upper surface, such that the height of the erase gate cap spacer from the surface to the substrate monotonically decreases from a peripheral region to a middle region. This concave shape helps optimize the electric field.
20. A flash memory device, comprising: a gate stack comprising a control gate separated from a floating gate by a control gate dielectric; an erase gate disposed on a first side of the gate stack; and a word line disposed on a second side of the gate stack that is opposite the first side, wherein the word line has a ledge portion at an outer side opposite to the gate stack and surrounding a tilted portion at an inner side closer to the gate stack; wherein the ledge portion has a planar upper surface and a reduced height smaller than a height of the tilted portion at the inner side of the word line.
A flash memory device contains a gate stack with a control gate, a floating gate, and a dielectric separating them. An erase gate is on one side of the gate stack, and a word line is on the other. The word line includes a flat ledge on its outer edge, away from the gate stack, surrounding a sloped or tilted region closer to the gate stack. The flat ledge has a lower height than the height of the tilted region at the inner side of the word line.
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June 3, 2015
May 9, 2017
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