A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6.
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1. A semiconductor device comprising: a first transistor; a second transistor; an inverter; and a capacitor, wherein the first transistor comprises an oxide semiconductor in a channel formation region, wherein a gate of the second transistor and a first terminal of the capacitor are electrically connected to a node, wherein one of a source and a drain of the second transistor is electrically connected to an input terminal of the inverter, wherein an output terminal of the inverter is electrically connected to an output terminal, wherein the node is configured to be supplied with a potential V 0 through the first transistor, wherein the node is configured to be brought into an electrically floating state by turning off the first transistor after the potential V 0 is supplied, wherein change in a potential V of the node with respect to time is expressed by Formula (1): V FN ( t ) = V 0 × ⅇ - ( t τ ) β , ( 1 ) where t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6.
A semiconductor device includes a first transistor with an oxide semiconductor channel, a second transistor, an inverter, and a capacitor. The gate of the second transistor and one terminal of the capacitor connect to a node. One of the second transistor's source/drain terminals connects to the inverter's input. The inverter's output is the device's output. The first transistor supplies a potential V0 to the node. After V0 is applied, the first transistor is turned off, putting the node into a floating state. The change in the node's potential (V) over time (t) follows the formula: V(t) = V0 * e^(-(t/τ)^β), where τ is a time constant, and β is a constant between 0.4 and 0.6. This measures a minute current by monitoring the voltage decay on the floating node.
2. The semiconductor device according to claim 1 , further comprising: a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor.
The semiconductor device from the previous description, which includes a first transistor with an oxide semiconductor channel, a second transistor, an inverter, and a capacitor, with the second transistor's gate and capacitor's terminal connected to a floating node, further includes a third transistor. One of the source/drain terminals of this third transistor is connected to one of the source/drain terminals of the second transistor. The change in the node's potential (V) over time (t) still follows the formula: V(t) = V0 * e^(-(t/τ)^β), where τ is a time constant, and β is a constant between 0.4 and 0.6. This third transistor provides additional control or signal processing capabilities.
3. The semiconductor device according to claim 1 , wherein the τ follows the Arrhenius equation.
The semiconductor device from the original description has a time constant (τ) in the voltage decay formula that follows the Arrhenius equation. The device includes a first transistor with an oxide semiconductor channel, a second transistor, an inverter, and a capacitor, with the second transistor's gate and capacitor's terminal connected to a floating node. The formula for node potential change is: V(t) = V0 * e^(-(t/τ)^β), where t is time, and β is between 0.4 and 0.6. The Arrhenius equation for τ suggests the voltage decay is temperature-dependent, enabling temperature-sensitive applications or characterization of temperature effects on the device.
4. The semiconductor device according to claim 1 , wherein an off-state current of the first transistor is obtained by measuring the change in the potential V FN over time.
The semiconductor device described earlier allows measuring the off-state current of the first transistor (with the oxide semiconductor channel) by observing the rate of change in the potential (V) of the floating node over time. The device includes a second transistor, an inverter, and a capacitor, where the second transistor's gate and capacitor's terminal connect to the node. By turning off the first transistor and monitoring how quickly the node voltage decays according to the formula V(t) = V0 * e^(-(t/τ)^β) (where t is time, τ is a constant, and β is between 0.4 and 0.6), the leakage current through the first transistor can be determined.
5. A memory device comprising the semiconductor device according to claim 1 .
A memory device incorporating the semiconductor device is described. The semiconductor device includes a first transistor with an oxide semiconductor channel, a second transistor, an inverter, and a capacitor, with the second transistor's gate and capacitor's terminal connected to a floating node. The first transistor supplies a potential V0 to the node, which then floats when the transistor turns off. The change in voltage over time follows the formula V(t) = V0 * e^(-(t/τ)^β) where t is time, τ is a time constant, and β is between 0.4 and 0.6. The memory function relies on storing charge on the capacitor and measuring its decay.
6. The memory device according to claim 5 , wherein data is retained for 10 years or longer at 85° C.
The memory device, which incorporates the semiconductor device (with its oxide semiconductor transistor, second transistor, inverter, capacitor, and floating node voltage decay characterized by V(t) = V0 * e^(-(t/τ)^β)), is capable of retaining stored data for at least 10 years when operating at a temperature of 85° C. This demonstrates long-term data storage capability even under elevated temperature conditions, making it suitable for applications requiring durable memory.
7. The memory device according to claim 5 , wherein data is retained for 100 years or longer at 85° C.
The memory device, which includes the semiconductor device (with its oxide semiconductor transistor, second transistor, inverter, capacitor, and floating node with voltage decay defined by V(t) = V0 * e^(-(t/τ)^β)), is capable of retaining stored data for at least 100 years at a temperature of 85° C. This exhibits exceptional data retention, indicating a highly stable charge storage mechanism within the memory cell.
8. An electronic device comprising: the memory device according to claim 5 ; and at least one of a microphone, a speaker, a display portion, and an operation key.
An electronic device is described that contains the memory device which incorporates a semiconductor device (with its oxide semiconductor transistor, second transistor, inverter, capacitor, and floating node voltage decay formula V(t) = V0 * e^(-(t/τ)^β)). The electronic device also contains at least one of the following components: a microphone, a speaker, a display portion, or an operation key. This indicates the memory device can be used in various consumer electronic applications that require data storage and user interaction.
9. A semiconductor device comprising: a plurality of cells arranged in a matrix, each of the cells comprising: a first transistor; a second transistor; an inverter; and a capacitor, wherein the first transistor comprises an oxide semiconductor in a channel formation region, wherein a gate of the second transistor and a first terminal of the capacitor are electrically connected to a node, wherein one of a source and a drain of the second transistor is electrically connected to an input terminal of the inverter, wherein an output terminal of the inverter is electrically connected to an output terminal, wherein the node is configured to be supplied with a potential V 0 through the first transistor, wherein the node is configured to be brought into an electrically floating state by turning off the first transistor after the potential V 0 is supplied, and wherein change in a potential V of the node over time is expressed by Formula (1): V FN ( t ) = V 0 × ⅇ - ( t τ ) β , ( 1 ) where t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6.
A semiconductor device is constructed from multiple memory cells arranged in a matrix. Each cell contains a first transistor using an oxide semiconductor channel, a second transistor, an inverter, and a capacitor. The gate of the second transistor and one terminal of the capacitor are connected to a node. One of the source/drain terminals of the second transistor is connected to the input terminal of the inverter, and the inverter's output connects to an output terminal. The node is supplied with a potential V0 through the first transistor, and then the node enters a floating state by turning off the first transistor. The change of potential V of the node over time is V(t) = V0 * e^(-(t/τ)^β), with t being time, τ a constant with time unit, and β between 0.4 and 0.6.
10. The semiconductor device according to claim 9 , further comprising: a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor.
The semiconductor device, comprising a matrix of memory cells (each with a first transistor using an oxide semiconductor channel, a second transistor, an inverter, and a capacitor connected to a floating node with voltage decay V(t) = V0 * e^(-(t/τ)^β)), further includes a third transistor in each cell. One of the source/drain terminals of the third transistor is electrically connected to one of the source/drain terminals of the second transistor. This additional transistor provides extra control over the memory cell, potentially enabling more complex read/write operations or improved performance.
11. The semiconductor device according to claim 9 , wherein the τ follows the Arrhenius equation.
In the semiconductor device comprising a matrix of memory cells (each with a first transistor using an oxide semiconductor channel, a second transistor, an inverter, and a capacitor connected to a floating node where voltage decays as V(t) = V0 * e^(-(t/τ)^β)), the time constant τ follows the Arrhenius equation. This indicates that the rate of voltage decay on the floating node is temperature-dependent, potentially impacting data retention and performance at different operating temperatures. The Arrhenius equation relates the time constant to temperature, allowing for modeling and prediction of device behavior under varying thermal conditions.
12. The semiconductor device according to claim 9 , wherein an off-state current of the first transistor is obtained by measuring the change in the potential V FN over time.
The semiconductor device, with its matrix of memory cells (each comprising a first transistor with an oxide semiconductor channel, a second transistor, an inverter, a capacitor, and a floating node whose voltage decays as V(t) = V0 * e^(-(t/τ)^β)), can be used to measure the off-state current of the first transistor. This measurement is performed by observing the change in the potential V of the floating node over time. By monitoring the rate of voltage decay when the first transistor is nominally off, the leakage current through the transistor can be quantified.
13. A memory device comprising the semiconductor device according to claim 9 .
A memory device incorporates the semiconductor device, which is made up of a matrix of memory cells. Each cell contains a first transistor using an oxide semiconductor channel, a second transistor, an inverter, and a capacitor. The gate of the second transistor and a terminal of the capacitor connect to a floating node. One of the source/drain terminals of the second transistor connects to the inverter's input, and the inverter's output is the cell output. The floating node's voltage decays according to V(t) = V0 * e^(-(t/τ)^β). The memory stores data based on charge retention in these cells.
14. The memory device according to claim 13 , wherein data is retained for 10 years or longer at 85° C.
The memory device, which includes the semiconductor device composed of memory cells with oxide semiconductor transistors, inverters, capacitors, and a floating node with a voltage decay of V(t) = V0 * e^(-(t/τ)^β), retains data for 10 years or longer at 85°C. This shows the memory is suitable for applications needing reliable data storage under harsh conditions.
15. The memory device according to claim 13 , wherein data is retained for 100 years or longer at 85° C.
The memory device, which includes the semiconductor device comprising memory cells with oxide semiconductor transistors, inverters, capacitors and a floating node with voltage decaying as V(t) = V0 * e^(-(t/τ)^β), retains data for 100 years or longer at 85°C. This extreme data retention means the memory can be used in very long-term archiving applications.
16. An electronic device comprising: the memory device according to claim 13 ; and at least one of a microphone, a speaker, a display portion, and an operation key.
An electronic device contains the memory device (composed of semiconductor cells with oxide semiconductor transistors, inverters, capacitors, and floating nodes where voltage decays as V(t) = V0 * e^(-(t/τ)^β)). The electronic device also contains at least one of a microphone, a speaker, a display, or an operation key. The memory can be used in a variety of consumer electronic devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 27, 2016
May 9, 2017
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