An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line. Partial linefill notification circuitry is used to provide partial linefill information to the atomic update handling circuitry during the linefill operation, and the atomic update handling circuitry is arranged to initiate the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line. This can provide a performance benefit, by avoiding the need for the atomic update handling circuitry to await completion of the linefill operation before beginning the atomic update operation.
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1. An apparatus comprising: a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines; atomic update handling circuitry to handle performance of an atomic update operation in respect of data at a specified address, the atomic update handling circuitry being arranged, when data at the specified address is stored within a cache line of the cache storage, to perform the atomic update operation on the data from that cache line; hazard detection circuitry to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address, the linefill operation causing the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line; partial linefill notification circuitry to provide partial linefill information to the atomic update handling circuitry during the linefill operation; and the atomic update handling circuitry being arranged to initiate the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line.
An apparatus efficiently handles atomic updates to data in a cache. The cache stores data accessible by processing circuitry, divided into cache lines. When an atomic update is needed for data at a specific address already in a cache line, dedicated circuitry performs the update directly on that cache line. If a "linefill" (cache update) is in progress to load data (including the target address) into the cache, the atomic update is initially deferred. However, special circuitry provides information about the partial linefill. The atomic update circuitry monitors this partial linefill data and starts the update as soon as the specific data at the target address becomes available, without waiting for the entire linefill to complete.
2. An apparatus as claimed in claim 1 , wherein: the partial linefill notification circuitry is arranged to provide the partial linefill information to the atomic update handling circuitry to identify when each data portion is available for the chosen cache line during the linefill operation; and the atomic update handling circuitry is arranged to determine from the partial linefill information when the linefill operation has progressed to a point where the data at the specified address is available for the chosen cache line.
Building upon the previous apparatus description, the partial linefill notification circuitry provides updates to the atomic update handling circuitry indicating the availability of each data portion as it arrives during the linefill. The atomic update handling circuitry then uses this information to determine precisely when the linefill has progressed far enough that the data required for the atomic update operation (at the specified address) is available in the chosen cache line, even if the entire linefill is not yet complete. This allows for very early initiation of the atomic update.
3. An apparatus as claimed in claim 1 , wherein the partial linefill notification circuitry is arranged to determine when the linefill operation has progressed to a point where the data portions available for the chosen cache line include the data at the specified address, and then to issue as the partial linefill information an indication that the data at the specified address is available for the chosen cache line.
In the apparatus, the partial linefill notification circuitry actively monitors the linefill operation. Once it determines that the arriving data portions include the specific data required for the atomic update operation (i.e., the data at the specified address), it sends a specific signal or indication confirming that the data at the specified address is now available. This signal acts as the partial linefill information, triggering the atomic update handling circuitry to begin the atomic update operation. The notification circuitry performs the checking rather than the atomic update circuitry.
4. An apparatus as claimed in claim 1 , wherein the partial linefill information comprises an address portion indicative of a corresponding data portion that is available for the chosen cache line during the linefill operation.
The partial linefill information provided to the atomic update handling circuitry includes address data. This address data indicates which specific data portion (of the sequence of data portions forming the complete cache line) is currently available during the linefill operation. By examining this address portion, the atomic update handling circuitry can determine whether the data at the specified address (needed for the atomic update) is now present and available within the incoming data.
5. An apparatus as claimed in claim 1 , wherein: the atomic update handling circuitry comprises a buffer having a plurality of buffer entries, each buffer entry for storing information relating to a pending operation; and the partial linefill information comprises an indication of the buffer entry for which the partial linefill information is being provided.
The atomic update handling circuitry contains a buffer with multiple entries, each entry storing details about a pending operation. The partial linefill information incorporates an indicator that identifies the specific buffer entry to which the linefill information relates. This allows the atomic update handling circuitry to associate the incoming partial linefill data with the correct pending atomic update operation, ensuring that the correct operation is initiated when its data becomes available.
6. An apparatus as claimed in claim 1 , further comprising: a data forwarding path coupled to the atomic update handling circuitry and arranged to provide to the atomic update handling circuitry, as at least part of the partial linefill information, the corresponding data portion that is available for the chosen cache line.
In addition to the partial linefill information, a direct data path connects to the atomic update handling circuitry. As part of the partial linefill process, the actual corresponding data portion that's becoming available for the chosen cache line is also forwarded to the atomic update handling circuitry. This means the data is available immediately to the atomic update circuitry, improving latency.
7. An apparatus as claimed in claim 6 , wherein the atomic update handling circuitry is incorporated within a load/store pipeline of the processing circuitry.
The apparatus incorporates the atomic update handling circuitry within the load/store pipeline of the main processing circuitry. This integration allows the atomic update operations to be handled efficiently alongside regular load and store operations, leveraging the existing pipeline infrastructure for faster processing.
8. An apparatus as claimed in claim 1 , wherein the atomic update operation comprises a read-modify-write operation, where the data at the specified address, as available for the chosen cache line, is obtained, a computation is performed to produce a modified data value, and the modified data value is written back to the chosen cache line.
The atomic update operation is implemented as a read-modify-write (RMW) operation. This involves reading the data from the specified address within the chosen cache line, performing a calculation or computation on the read data to generate a modified data value, and then writing the modified data value back into the same location in the chosen cache line.
9. An apparatus as claimed in claim 8 , wherein the atomic update operation is an atomic load operation where, in addition to the read-modify-write operation, the obtained data at the specified address is output to the processing circuitry.
The atomic update operation from the previous description is a special type of atomic load operation. It performs the read-modify-write operation (reading data, modifying it, and writing it back), but *also* outputs the original data that was read to the main processing circuitry. This allows the processor to use the original value in further calculations or operations.
10. An apparatus as claimed in claim 1 , wherein the atomic update operation comprises obtaining the data at the specified address as available for the chosen cache line, performing a computation to produce a result value, and selectively writing a modified data value back to the chosen cache line dependent on the result value.
The atomic update operation involves obtaining data from the specified address within the cache line and performing a computation to produce a result value. The apparatus then selectively writes a modified data value back to the chosen cache line, and this write-back is conditional, depending on the computed result. The system might choose *not* to write back data, depending on the result of the computation.
11. An apparatus as claimed in claim 1 , further comprising cache access circuitry to store the data into the chosen cache line during the linefill operation.
The apparatus includes cache access circuitry. During the linefill operation, this circuitry is responsible for actually storing the received data into the correct location within the chosen cache line. This circuitry manages the physical writing of the incoming data portions into the cache memory.
12. An apparatus as claimed in claim 11 , wherein the cache access circuitry is arranged, whilst the atomic update operation is being performed, to lock the chosen cache line from being accessed at least for any operations that could compromise atomicity of the atomic update operation.
While an atomic update operation is in progress, the cache access circuitry locks the chosen cache line. This lock prevents other operations from accessing the cache line while the atomic update is being performed, ensuring the atomicity (indivisibility) of the operation. The lock prevents any actions that might interfere with the data consistency of the atomic update.
13. An apparatus as claimed in claim 12 , wherein the cache access circuitry is arranged, whilst the atomic update operation is being performed, to lock the chosen cache line from being accessed for any snoop operations.
Expanding on the cache line locking, while an atomic update is happening, the cache access circuitry also prevents snoop operations from accessing the locked cache line. Snooping is a mechanism where other caches or devices can observe and potentially invalidate data. By blocking snoops, the atomicity of the update is further protected.
14. An apparatus as claimed in claim 1 , wherein the atomic update handling circuitry is provided within store buffer circuitry used to process store operations requested by the processing circuitry.
The atomic update handling circuitry is implemented within the store buffer circuitry. The store buffer is a component used to manage store operations requested by the processing circuitry. By integrating the atomic update functionality into the store buffer, store operations, including atomic updates, can be handled in a unified and efficient manner.
15. An apparatus as claimed in claim 1 , wherein the atomic update handling circuitry is arranged, when data at the specified address is determined not to be stored within a cache line of the cache storage and there is no pending linefill operation for the cache storage that will cause a chosen cache line to be populated with data that includes data at the specified address, to output the atomic update operation for handling by components external to the apparatus.
If the data for the specified address is *not* found in any cache line and there's *no* linefill operation in progress that will bring that data into the cache, then the atomic update handling circuitry forwards the atomic update operation to external components or systems for handling. This allows the apparatus to handle atomic updates to data residing outside of the local cache.
16. An apparatus as claimed in claim 1 , wherein the data at the specified address is available for the chosen cache line once it has been stored within the chosen cache line.
The data at the specified address is considered available for the chosen cache line once it has been physically stored inside that cache line. This is the most basic definition of availability: when the data has been written to the correct location in the cache memory.
17. An apparatus as claimed in claim 1 , wherein the data at the specified address is available for the chosen cache line once it has been locally buffered within the apparatus for storing within the chosen cache line.
The data at the specified address is considered available for the chosen cache line when it has been buffered locally within the apparatus, even if it hasn't been written to the cache line itself yet. This means the data is ready and waiting to be written, allowing the atomic update to begin sooner than waiting for the actual write to complete.
18. A method of handling atomic update operations within an apparatus having a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines, the method comprising: employing atomic update handling circuitry to handle performance of the atomic update operation in respect of data at a specified address, the atomic update handling circuitry being arranged, when data at the specified address is stored within a cache line of the cache storage, to perform the atomic update operation on the data from that cache line; triggering deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address; performing the linefill operation to cause the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line; providing partial linefill information to the atomic update handling circuitry during the linefill operation; and initiating the atomic update operation responsive to the atomic update handling circuitry detecting from the partial linefill information that the data at the specified address is available for the chosen cache line.
A method for efficiently handling atomic updates in a cache-equipped device. The method employs dedicated atomic update handling circuitry that performs the update if the needed data is already in a cache line. If a linefill is occurring to load the data, the atomic update is initially delayed. During the linefill, partial linefill information is provided to the atomic update circuitry. This circuitry monitors the partial linefill information and initiates the atomic update as soon as the relevant data at the target address becomes available, avoiding the need to wait for full linefill completion.
19. An apparatus comprising: cache storage means for storing data for access by processing circuitry, the cache storage means having a plurality of cache lines; atomic update handling means for handling performance of an atomic update operation in respect of data at a specified address, the atomic update handling means, when data at the specified address is stored within a cache line of the cache storage means, for performing the atomic update operation on the data from that cache line; hazard detection means for triggering deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage means is pending that will cause a chosen cache line to be populated with data that includes data at the specified address, the linefill operation causing the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line; partial linefill notification means for providing partial linefill information to the atomic update handling means during the linefill operation; and the atomic update handling means for initiating the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line.
An apparatus includes: a cache storage means for storing data and dividing it into cache lines; atomic update handling means for performing atomic update operations when the targeted data resides in a cache line; hazard detection means for pausing atomic updates when a linefill operation is in progress; partial linefill notification means for reporting on the progress of the linefill operation; and, the atomic update handling means, which begins the atomic update as soon as the partial linefill information indicates the relevant data at the specified address is available, without waiting for the complete linefill.
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November 27, 2015
May 16, 2017
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