Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
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1. A circuit comprising: a transmit clock tree configured to receive a clock signal and to feed the clock signal to a first plurality of nodes; and a receive clock tree feeding a second plurality of nodes, wherein the transmit clock tree is configured to forward the clock signal to the receive clock tree; wherein individual nodes on the transmit clock tree correspond to respective individual nodes on the receive clock tree, each clock tree being unbalanced and providing matched insertion delays for corresponding nodes at the transmit and receive clock trees.
A circuit for die-to-die clock distribution includes a "transmit clock tree" on one die that sends a clock signal to multiple points (nodes). A "receive clock tree" on another die also feeds a clock signal to multiple nodes. The transmit clock tree provides the clock signal to the receive clock tree. Each node on the transmit clock tree has a corresponding node on the receive clock tree. Both clock trees are designed to be unbalanced, meaning the clock signal takes different amounts of time to reach each node within a single tree. However, corresponding nodes on the transmit and receive trees experience the *same* clock arrival time (insertion delay).
2. The circuit of claim 1 , wherein the corresponding nodes are connected across two dies by data routes, wherein the data routes are of a uniform length.
The die-to-die clock distribution circuit from the previous description has corresponding nodes on the transmit and receive clock trees that are connected across the two dies using data routes. These data routes connecting corresponding nodes all have the *same* physical length. This ensures that any signal traveling between corresponding nodes experiences a consistent delay due to the connection itself.
3. The circuit of claim 1 , wherein the first plurality of nodes and the second plurality of nodes are configured to receive the same clock signal.
In the die-to-die clock distribution circuit described previously, the nodes on the transmit and receive clock trees all receive the *same* original clock signal. This suggests the transmit clock tree acts as a driver or repeater to distribute the clock signal across the two dies.
4. The circuit of claim 1 , wherein the transmit clock tree is configured to provide the clock signal to the individual nodes of the first plurality of nodes with different insertion delays relative to each other, wherein an insertion delay for a given node of the first plurality of nodes includes a propagation delay from a time the clock signal rises at a start node of the transmit clock tree to a time the clock rises at a flip flop of the given node.
In the die-to-die clock distribution circuit described previously, the transmit clock tree provides the clock signal to its nodes with *different* insertion delays. Insertion delay is the time it takes for the clock signal to travel from the start of the clock tree to a flip-flop at each node. This means some flip-flops on the first die receive the clock signal sooner than others.
5. The circuit of claim 1 , wherein the receive clock tree is configured to provide the clock signal to the individual nodes of the second plurality of nodes with different insertion delays relative to each other, wherein an insertion delay for a given node bit of the second plurality of nodes includes a propagation delay from a time the clock signal rises at a start node of the receive clock tree to a time the clock signal rises at a flip flop of the given node.
In the die-to-die clock distribution circuit described previously, the receive clock tree provides the clock signal to its nodes with *different* insertion delays. Insertion delay is the time it takes for the clock signal to travel from the start of the clock tree to a flip-flop at each node. This means some flip-flops on the second die receive the clock signal sooner than others. The insertion delays are matched to the transmit side.
6. The circuit of claim 1 , wherein the transmit clock tree has non-uniform route lengths from a start node of the transmit clock tree to each of the first plurality of nodes, and wherein the receive clock tree has non-uniform route lengths from a start node of the receive clock tree to each of the second plurality of nodes.
In the die-to-die clock distribution circuit described previously, the transmit clock tree has varying wire lengths from the clock tree's starting point to each node. Similarly, the receive clock tree also has varying wire lengths from its starting point to each node. The non-uniform route lengths contribute to the differing insertion delays at each node, which are matched between corresponding nodes on the two dies.
7. The circuit of claim 1 , wherein each node of the first plurality of nodes includes a flip-flop, further wherein each node of the second plurality of nodes includes a flip-flop.
In the die-to-die clock distribution circuit described previously, each node on both the transmit and receive clock trees includes a flip-flop. This indicates that the purpose of the clock trees is to provide clock signals to the flip-flops on both dies, allowing them to synchronize data transfer.
8. The circuit of claim 1 , wherein the transmit clock tree is included in a first die and wherein the receive clock tree is included in a second die, further wherein the first die and second die are disposed in a multi-die package, the package comprising: a substrate upon which the first and second die are disposed; a plurality of metal layers providing electrical communication between the first die and second die and with external pins of the package; and dielectric layers over the first die and second die.
In the die-to-die clock distribution circuit described previously, the transmit clock tree is on one silicon die, and the receive clock tree is on another. These dies are housed in a multi-die package. The package includes a substrate that the dies sit on, metal layers that provide electrical connections between the dies and to external pins, and insulating dielectric layers.
9. The circuit of claim 1 , wherein the transmit clock tree is included in a first die and wherein the receive clock tree is included in a second die, further wherein the first die and second die are in electrical communication with each other through an interposer, further wherein the first die and second die and the interposer are included in a multi-die package.
In the die-to-die clock distribution circuit described previously, the transmit clock tree resides on a first silicon die, and the receive clock tree is on a second. The dies communicate via an interposer. The interposer and the two dies are inside a multi-die package.
10. A method comprising: providing a clock to a first plurality of nodes on a first die and to a second plurality of nodes on a second die, where individual ones of the first plurality of nodes correspond to respective ones of the nodes on the second die; and for each one of the first plurality of nodes: receiving the clock having an insertion delay; and transmitting data to a flip-flop at a corresponding node at the second die in response to receiving the clock, the flip-flop at the corresponding node at the second die receiving the clock with substantially the same insertion delay; wherein a clock tree of the first die, providing the clock to the first plurality of nodes, has non-uniform insertion delays of the clock; and wherein a clock tree of the second die, providing the clock to the second plurality of nodes, has non-uniform insertion delays of the clock.
A method for clocking a die-to-die interface involves providing a clock signal to nodes on two dies. Each node on the first die has a corresponding node on the second. The clock signal arrives at each node on the first die after a certain insertion delay. Data is then transmitted to the corresponding node on the second die. The key is that the clock signal *also* arrives at the corresponding node on the second die with *almost* the same insertion delay. The clock trees on each die intentionally have *different* delays to each node.
11. The method of claim 10 , wherein a plurality of pairs of the corresponding nodes are connected from the first die to the second die using metal routes that have a uniform length.
The clocking method from the previous description also involves connecting pairs of corresponding nodes (one on each die) with metal wires of the *same* length. This ensures that the signal propagation time between corresponding nodes is uniform, helping to maintain timing synchronization between the two dies.
12. The method of claim 11 , further comprising: transmitting the clock from a clock node on the clock tree of the first die to a clock node on the clock tree of the second die, wherein a metal route between the clock node on the clock tree of the first die to the clock node on the clock tree of the second die has the uniform length.
The clocking method previously described includes transmitting the clock signal itself between the transmit and receive clock trees using metal routes of the uniform length. This specifies that not only data routes between corresponding nodes, but also the clock signal path connecting the trees, should maintain consistent length.
13. The method of claim 10 , further comprising for each one of the second plurality of nodes: capturing the data by the flip-flop at the corresponding node at the second die in response to receiving the clock.
The clocking method described previously also includes capturing data by a flip-flop at the corresponding node on the second die in response to receiving the clock signal. This clarifies the data transfer process, where the flip-flop uses the clock signal's arrival to latch the incoming data.
14. The method of claim 10 , wherein the individual nodes of the first plurality of nodes have different insertion delays relative to each other.
The clocking method previously described specifies that individual nodes on the first die (driven by the transmit clock tree) have *different* clock insertion delays relative to each other. This highlights the intentional use of an unbalanced clock tree.
15. The method of claim 10 , wherein the individual nodes of the second plurality of nodes have different insertion delays relative to each other.
The clocking method previously described specifies that individual nodes on the second die (driven by the receive clock tree) have *different* clock insertion delays relative to each other. This highlights the intentional use of an unbalanced clock tree and the need to match delays with the transmit die.
16. The method of claim 10 , wherein the first die and the second die are in communication with each other through an interposer.
The clocking method described previously includes a first die and a second die that communicate via an interposer. The interposer provides an electrical pathway between the two dies for data and clock signals.
17. The method of claim 10 , wherein the first die and the second die are included in a same multi-die package.
The clocking method described previously includes a first die and a second die that are included in the same multi-die package. This indicates that the two dies are closely integrated within a single package, facilitating high-speed communication.
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April 25, 2016
May 16, 2017
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