A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
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1. A semiconductor memory apparatus comprising: a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
A semiconductor memory apparatus has column and row address decoders that select memory cells. A driving driver provides different voltages to resistive memory elements based on the column selection. A sink current control unit creates multiple sink voltages, and current sink units draw current from memory elements to ground based on these sink voltages. The driving driver dictates voltage levels, and the current sink units control current flow, facilitating data reading and writing in the memory array.
2. The semiconductor memory apparatus according to claim 1 , wherein the driving driver unit comprises: a driving driver configured to provide a driving voltage in response to the column select signal; and a plurality of first resistor elements electrically coupled in series to voltage-divide an output of the driving driver, and wherein a lower voltage is provided to a resistive memory element distant from the driving driver rather than to a resistive memory element close to the driving driver.
In the semiconductor memory apparatus, the driving driver unit uses a driving driver and a series of resistors to provide different voltages. Resistive memory elements closer to the driving driver receive higher voltages, while those further away receive lower voltages. This voltage division compensates for voltage drop across the memory array, ensuring more uniform voltage levels seen by each memory cell, leading to better read/write performance. This design improves uniformity in memory element behavior, by applying progressively diminishing voltages.
3. The semiconductor memory apparatus according to claim 2 , wherein the plurality of resistive memory elements are respectively electrically coupled to nodes where the plurality of first resistor elements electrically coupled in series are electrically coupled with each other.
The semiconductor memory apparatus with series resistors supplying different voltages to memory elements, features resistive memory elements connected at the nodes between these series resistors. Each memory element taps into the voltage divider at a different point, receiving a distinct voltage level based on its location relative to the driving driver. This configuration ensures fine-grained voltage control for individual memory cells, optimizing performance.
4. The semiconductor memory apparatus according to claim 3 , wherein a read write circuit unit is electrically coupled to a node where a last resistor element, most distant from the driving driver, among the plurality of first resistor elements electrically coupled in series and a resistor memory element are electrically coupled.
In the semiconductor memory apparatus, where series resistors provide graded voltages to resistive memory elements, a read/write circuit is connected at the farthest resistor. Specifically, the read/write circuit is linked to the node where the last resistor in the series and the corresponding memory element are connected. This placement facilitates sensing and writing data to the memory element with the lowest driving voltage.
5. The semiconductor memory apparatus according to claim 2 , wherein the sink current control unit provides a sink voltage with a higher voltage level to a current sink unit which is electrically coupled with a resistive memory element, as a distance between the driving driver and any one of resistive memory element of the plurality of resistive memory elements increases.
In the semiconductor memory apparatus, the sink current control unit provides higher sink voltages to current sink units connected to resistive memory elements farther from the driving driver. This compensation balances current flow and ensures consistent read/write margins across the memory array, since elements farther away also received lower driving voltages, this configuration is important. The higher voltage sink allows greater current flow from more remote memory elements.
6. The semiconductor memory apparatus according to claim 5 , wherein the sink current control unit generates the plurality of sink voltages with voltage levels between a first word line driving voltage and a second word line driving voltage, and wherein the sink current control unit outputs a sink voltage selected among the plurality of sink voltages in response to the word line select signal.
The sink current control unit in the semiconductor memory apparatus creates sink voltages between first and second word line driving voltages. It selects a sink voltage from these levels based on the word line select signal. This selection allows tailored current sinking for different memory elements, ensuring proper read/write behavior within a range of voltage levels. The sink current control unit outputs a pre-selected sink voltage.
7. The semiconductor memory apparatus according to claim 6 , wherein the sink current control unit is applied with the first and second word line driving voltages on both ends of a plurality of second resistor elements which are electrically coupled in series, and wherein the sink current control unit includes a plurality of switching sections which output voltages of nodes where the plurality of second resistor elements are electrically coupled, in response to the word line select signal.
The sink current control unit in the semiconductor memory apparatus uses a series of resistors connected to the first and second word line driving voltages at either end. Switching sections select voltages from the nodes between these series resistors, responding to the word line select signal. This resistor ladder creates multiple sink voltage levels, and the switching sections route the appropriate voltage to the corresponding current sink unit.
8. A semiconductor memory apparatus comprising: a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements, respectively, in response to a column select signal; a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to a plurality of sink voltages; and a sink current control unit configured to generate the plurality of sink voltages with different voltage levels in response to a plurality of word line select signals.
A semiconductor memory apparatus has a driving driver unit that supplies different voltages to resistive memory elements based on the column select signal. Current sink units draw current from memory elements to ground based on sink voltages. A sink current control unit generates these sink voltages based on a set of word line select signals. This design allows independent control of the driving voltage and current sinking for each memory element, optimizing memory performance and power consumption.
9. The semiconductor memory apparatus according to claim 8 , wherein the driving driver unit comprises: a driving driver configured to provide a driving voltage in response to the column select signal, and wherein the voltages with different voltage levels are provided to the plurality of respective resistive memory elements according to distances between the driving driver and the plurality of respective resistive memory elements.
The semiconductor memory apparatus uses a driving driver to supply a driving voltage depending on the column select signal. The different voltage levels supplied to resistive memory elements depend on their distance from the driving driver. This accounts for voltage drops and allows memory elements further from the driver to function as expected.
10. The semiconductor memory apparatus according to claim 9 , wherein the driving driver unit provides a voltage with a lower voltage level to a resistive memory element distant from the driving driver rather than to a resistive memory element close to the driving driver.
The semiconductor memory apparatus with graded driving voltages supplies lower voltages to resistive memory elements that are farther away from the driving driver. This intentional voltage drop compensation ensures that all memory elements, regardless of their physical location, receive sufficient voltage to operate correctly during read and write operations. The driving driver provides voltage correction.
11. The semiconductor memory apparatus according to claim 9 , wherein the plurality of current sink units are configured such that a current sink unit electrically coupled with a resistive memory element distant from the driving driver is applied with a sink voltage with a higher voltage level than a current sink unit electrically coupled with a resistive memory element close to the driving driver.
In the semiconductor memory apparatus, current sink units connected to resistive memory elements farther from the driving driver receive higher sink voltages. This balances current flow and compensates for the lower driving voltages supplied to these distant memory elements, ensuring consistent read/write margins across the memory array. Higher sink voltages are assigned to more remote resistive memory elements.
12. The semiconductor memory apparatus according to claim 9 , wherein the sink current control unit outputs one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.
The sink current control unit in the semiconductor memory apparatus selects and outputs one sink voltage from a set of possible voltages, based on the active word line select signal. The correct sink voltage is applied from a range of potentials, to maintain correct current flow out of each memory element.
13. The semiconductor memory apparatus according to claim 12 , wherein the sink current control unit is configured to provide a sink voltage with a higher voltage level to a current sink unit electrically coupled with the resistive memory element distant from the driving driver than a current sink unit electrically coupled with the resistive memory element close to the driving driver.
In the semiconductor memory apparatus, the sink current control unit provides a higher sink voltage to the current sink unit connected to a resistive memory element farther from the driving driver. This difference in sink voltage ensures that more remote resistive memory elements can perform operations at voltages similar to the other resistive memory elements.
14. The semiconductor memory apparatus according to claim 13 , wherein the sink current control unit comprises: a voltage supply signal generating section configured to generate a voltage supply signal when even one of the plurality of word line select signals is enabled; a voltage dividing section configured to supply a first word line driving voltage and a second word line driving voltage to both ends, respectively, of a plurality of resistor elements electrically coupled in series, in response to the voltage supply signal, and generate the plurality of sink voltages; and a plurality of switching sections configured to output one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.
The sink current control unit features a voltage supply signal generator which activates when any word line select signal is enabled. A voltage divider uses a series of resistors to supply the first and second word line driving voltages. It generates a set of sink voltages in response to the supply signal. Switching sections select one of these sink voltages based on the enabled word line select signal.
15. A semiconductor memory apparatus comprising: a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal; a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and a sink current control unit configured to control the plurality of current sink units to flow different amounts of current from the plurality of current sink units to the ground terminal.
A semiconductor memory apparatus has a driving driver unit that provides varying voltages to resistive memory elements depending on a column select signal. Current sink units draw current from the resistive memory elements to ground depending on word line select signals. A sink current control unit regulates the current flow from the current sink units to ground, enabling current level control.
16. The semiconductor memory apparatus according to claim 15 , wherein the driving driver unit comprises: a driving driver configured to provide a driving voltage in response to the column select signal; and a plurality of resistor elements electrically coupled in series to be inputted with an output of the driving driver, and wherein the resistive memory elements are electrically coupled to respective nodes where the plurality of resistor elements are electrically coupled.
In the semiconductor memory apparatus, the driving driver unit has a driving driver that responds to the column select signal. A series of resistor elements are connected to the driver output. Resistive memory elements are connected to the nodes between these resistors. The resistors provide different voltages to resistive memory elements according to where in the series of resistors they are coupled.
17. The semiconductor memory apparatus according to claim 16 , wherein the plurality of current sink units are electrically coupled to the plurality of respective resistive memory elements, and wherein one of the plurality of current sink units is activated in response to the plurality of word line select signals.
The semiconductor memory apparatus features current sink units connected to the resistive memory elements. The word line select signals activate one of the current sink units. Only one current sink unit and one memory element connected to it are active at any given time, and that activation is controlled by the set of word line select signals.
18. The semiconductor memory apparatus according to claim 17 , wherein the current sink control unit differentiates amounts of current flowed by the plurality of current sink units electrically coupled to the plurality of respective resistive memory elements, according to respective distances between the driving driver and the plurality of resistive memory elements.
In the semiconductor memory apparatus, the current sink control unit differentiates current flow from current sink units depending on the distance between the driving driver and the resistive memory elements. This ensures more stable current flow overall, despite variations in the distance between the driving driver and the resistive memory elements.
19. The semiconductor memory apparatus according to claim 18 , wherein the current sink control unit is configured such that an amount of current flowed from a current sink unit electrically coupled with a resistive memory element close to the driving driver, to the ground terminal, is smaller than an amount of current flowed from a current sink unit electrically coupled with a resistive memory element distant from the driving driver.
The current sink control unit is set up so that the current from a current sink unit that is electrically coupled to a nearby resistive memory element, flows less strongly to ground than the current from a distant resistive memory element. This accounts for voltage drops in the driving voltage, and makes for more stable operations.
20. The semiconductor memory apparatus according to claim 19 , wherein the current sink control unit comprises a plurality of resistor elements which are electrically coupled in series, and wherein the plurality of resistor elements comprised within the driving driver unit or the current sink control unit are electrically coupled to the plurality of current sink units, and the ground terminal is electrically coupled to a resistor element which is farthest from the driving driver.
The current sink control unit contains a series of resistors. The driving driver unit and the current sink control unit resistors connect to current sink units. The farthest resistor is connected to ground. The series of resistors provides differential current flow to the ground connection in order to account for location of the current sink unit.
21. A microprocessor, comprising: a control unit configured to receive a signal including a command from the outside; an operation unit configured to perform an operation according to a decryption result of the command in the control unit; and a storage unit configured to store one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated, wherein the storage unit includes a semiconductor memory apparatus comprises: a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of respective resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
A microprocessor includes a control unit, an operation unit, and a storage unit. The storage unit incorporates a semiconductor memory apparatus with column and row address decoders, a driving driver providing different voltages to resistive memory elements based on column selection, a sink current control unit generating sink voltages, and current sink units drawing current from memory elements to ground based on these sink voltages. The memory enables the microprocessor to store and retrieve data efficiently.
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November 15, 2013
May 23, 2017
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