Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit, comprising: a memory array defined by a plurality of memory cells arranged in rows and columns to form the memory array, each column including a first group of transistors and a second group of transistors; a plurality of gate terminals shared between adjacent columns of the memory cells; a plurality of inversion stages formed of memory cells modified from the memory cells only in a single one of the columns, the single one of the columns being a middle column among the adjacent columns of the memory cells, gate terminals of the first group of transistors of the middle column being directly coupled only with corresponding gate terminals of the second group of transistors of an adjacent column within the same row, the inversion stages being connected in a loop to form a ring oscillator; and a speed determination circuit configured to determine a speed of the memory cells based on a frequency of the ring oscillator.
An integrated circuit includes a memory array made of memory cells arranged in rows and columns. Columns share gate terminals. A ring oscillator is formed from modified memory cells in one column (the middle column, if there are adjacent columns). The gate terminals of one transistor group in the middle column are connected to corresponding gate terminals of another transistor group in an adjacent column within the same row. These modified memory cells are connected in a loop creating a ring oscillator. A speed determination circuit measures the ring oscillator's frequency to determine the memory cells' speed.
2. The integrated circuit of claim 1 , wherein at least (i) a first gate terminal of a first transistor in a first column and (ii) a second gate terminal of a second transistor in a second column adjacent to the first column are coupled together and connected to a common word line of the integrated circuit.
The integrated circuit that includes a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, has the following feature: A gate terminal of a transistor in one column and a gate terminal of a transistor in the adjacent column are connected together and to a shared word line.
3. The integrated circuit of claim 1 , wherein differential outputs of an inversion stage of the inversion stages in a row of the one of the columns are connected to differential inputs of a next inversion stage of the inversion stages in a next row of the one of the columns.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, the differential outputs of an inversion stage in a row of the single column are connected to the differential inputs of the next inversion stage in the next row of the same column. This connects the inversion stages vertically.
4. The integrated circuit of claim 3 , wherein a source terminal of a first transistor and a drain terminal of a second transistor are grounded, both first and second transistors being in the inversion stage.
The integrated circuit that includes a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, and where differential outputs of an inversion stage are connected to differential inputs of the next inversion stage in the next row, further includes: a source terminal of a first transistor and a drain terminal of a second transistor in the inversion stage are grounded.
5. The integrated circuit of claim 1 , wherein each inversion stage is configured to generate a pair of differential outputs that are inputted to gate terminals of transistors in a next inversion stage.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, each inversion stage generates a pair of differential outputs that are then fed into the gate terminals of transistors in the following inversion stage. This facilitates signal propagation through the ring oscillator.
6. The integrated circuit of claim 1 , further comprising: an adaptive voltage scaling module configured to generate a feedback signal having a characteristic that is varied based on the frequency of the ring oscillator, the feedback signal being provided to a voltage regulator to cause the voltage regulator to adjust a supply voltage that is supplied to the memory array based on the feedback signal.
The integrated circuit that includes a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, also includes an adaptive voltage scaling module. This module generates a feedback signal, which changes based on the ring oscillator's frequency. This feedback signal is sent to a voltage regulator. The voltage regulator adjusts the supply voltage to the memory array based on the feedback signal. This allows the memory to dynamically adjust its voltage based on speed.
7. The integrated circuit of claim 1 , wherein a memory cell includes two pass transistors coupled to bit lines, and a latch formed by two cross-coupled inverters of the memory cell.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, each memory cell is comprised of two pass transistors connected to bit lines, and a latch formed by two cross-coupled inverters.
8. The integrated circuit of claim 1 , wherein the plurality of inversion stages are formed of memory cells modified from the plurality of memory cells sharing bit lines such that characteristics of the inversion stages are substantially same as characteristics of the memory cells and that the frequency of the ring oscillator is indicative of a speed of the memory array.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, the inversion stages use memory cells (sharing bit lines with other memory cells) that are modified, so their characteristics are essentially the same as the regular memory cells. Therefore, the ring oscillator's frequency closely reflects the actual speed of the memory array.
9. The integrated circuit of claim 1 , wherein the ring oscillator includes an odd number of the modified memory cells in the one of the columns.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, the ring oscillator contains an odd number of modified memory cells in the single column. This ensures the oscillation can occur by guaranteeing there isn't an even number of inversions causing a stable output.
10. The integrated circuit of claim 1 , wherein the speed determination circuit is configured to count a number of inversions during a time interval to determine the frequency of the ring oscillator.
In the integrated circuit including a memory array made of memory cells arranged in rows and columns, a ring oscillator formed from modified memory cells in a single column, and a speed determination circuit to measure the memory cells' speed based on the ring oscillator's frequency, the speed determination circuit counts the number of inversions that occur within a specified time interval. This count is then used to calculate the ring oscillator's frequency.
11. A method for determining a speed of memory cells, comprising: operating a memory array in an integrated circuit, the memory array defined by a plurality of memory cells arranged in rows and columns, the memory array including a plurality of gate terminals shared between adjacent columns of the memory cells, each column including a first group of transistors and a second group of transistors; measuring a frequency of a ring oscillator formed by a plurality of inversion stages that are formed of memory cells modified from the memory cells only in a single one of the columns, the single one of the columns being a middle column among the adjacent columns of the memory cells, gate terminals of the first group of transistors of the middle column being directed coupled on with corresponding gate terminals of the second group of transistors of an adjacent column within the same row, the inversion stages being connected in a loop to form the ring oscillator; and determining a speed of the memory cells based on the measured frequency of the ring oscillator.
A method for determining the speed of memory cells in an integrated circuit. The method involves operating a memory array, made of memory cells arranged in rows and columns sharing gate terminals. Measure the frequency of a ring oscillator, which is formed from modified memory cells in one of the columns (the middle column if adjacent columns exist). The gate terminals of one transistor group in the middle column directly connect to corresponding gate terminals of another transistor group in an adjacent column in the same row. These inversion stages connect in a loop creating the ring oscillator. Finally, determine the memory cells' speed based on the measured ring oscillator frequency.
12. The method of claim 11 , further comprising: operating at least (i) a first gate terminal of a first transistor in a first column and (ii) a second gate terminal of a second transistor in a second column adjacent to the first column are coupled together and connected to a common word line of an integrated circuit.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: operating at least (i) a first gate terminal of a first transistor in a first column and (ii) a second gate terminal of a second transistor in a second column adjacent to the first column such that they are coupled together and connected to a common word line of the integrated circuit.
13. The method of claim 11 , further comprising: feeding differential outputs of an inversion stage of the inversion stages in a row of the one of the columns into differential inputs of a next inversion stage of the inversion stages in a next row of the one of the columns.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: feeding differential outputs from an inversion stage in a row of the single column into differential inputs of a next inversion stage in a next row of the same column.
14. The method of claim 13 , further comprising: grounding a source terminal of a first transistor and a drain terminal of a second transistor, both first and second transistors being in the inversion stage.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, determining the speed of the memory cells based on the measured frequency of the ring oscillator, and feeding differential outputs from an inversion stage into differential inputs of a next inversion stage in the next row, further includes: grounding the source terminal of a first transistor and the drain terminal of a second transistor within the inversion stage.
15. The method of claim 11 , further comprising: generating, by each inversion stage, a pair of differential outputs that are inputted to gate terminals of transistors in a next inversion stage.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: generating a pair of differential outputs from each inversion stage, which are then inputted into the gate terminals of transistors in the next inversion stage.
16. The method of claim 11 , further comprising: generating, by an adaptive voltage scaling module, a feedback signal having a characteristic that is varied based on the measured frequency of the ring oscillator; and providing the feedback signal to a voltage regulator to cause the voltage regulator to adjust a supply voltage that is supplied to the memory array based on the feedback signal.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, also includes generating a feedback signal using an adaptive voltage scaling module. The feedback signal's characteristics change based on the ring oscillator's frequency. This feedback signal is then sent to a voltage regulator, causing it to adjust the supply voltage to the memory array based on the feedback.
17. The method of claim 11 , further comprising: operating a memory cell including (i) two pass transistors coupled to bit lines and (ii) a latch formed by two cross-coupled inverters of the memory cell.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: operating a memory cell which includes two pass transistors connected to bit lines and a latch formed by two cross-coupled inverters.
18. The method of claim 11 , further comprising: operating the plurality of inversion stages formed of memory cells that are modified from the plurality of memory cells sharing bit lines such that characteristics of the inversion stages are substantially same as characteristics of the memory cells and that the frequency of the ring oscillator is indicative of the speed of the memory array.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: operating the inversion stages such that they are made of memory cells which are modified from the original memory cells sharing bit lines. This ensures that the characteristics of the inversion stages are substantially the same as the characteristics of the memory cells, so the ring oscillator frequency is a reliable indicator of the memory array's speed.
19. The method of claim 11 , further comprising: operating the ring oscillator including an odd number of the modified memory cells in the one of the columns.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: operating the ring oscillator with an odd number of modified memory cells in the single column.
20. The method of claim 11 , further comprising: counting a number of inversions during a time interval to measure the frequency of the ring oscillator.
The method for determining the speed of memory cells by operating a memory array, measuring the frequency of a ring oscillator formed from modified memory cells in a single column, and determining the speed of the memory cells based on the measured frequency of the ring oscillator, further includes: counting the number of inversions during a set time interval to measure the ring oscillator's frequency.
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August 26, 2015
June 6, 2017
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