One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
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1. An article of manufacture comprising a memory circuit comprising: volatile output circuitry (VOC); and a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising: a first anti-fuse device; a second anti-fuse device; a first select device connected in series with the first anti-fuse device at a first node; a second select device connected in series with the second anti-fuse device at a second node; a first pass device connected between the first node and a VOC input node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the VOC input node; and a second pass device connected between the second node and the VOC input node and usable to selectively pass a voltage at the second node to the VOC input node, wherein the volatile output circuitry is connected to receive the NVM output signal from the NVM cell at the VOC input node and generate a VOC output signal indicative of the program state of the NVM cell.
A memory circuit includes volatile output circuitry (VOC) and a programmable non-volatile memory (NVM) cell. The NVM cell stores data using two anti-fuses and generates an output signal (NVM output) based on its programmed state. Each anti-fuse is connected in series with a select transistor. Two pass transistors connect each anti-fuse/select transistor pair to the VOC input. By selectively blowing one or both anti-fuses, the NVM cell provides a specific voltage level to the VOC input. The VOC then generates a VOC output signal reflecting the programmed state of the NVM cell.
2. The article of claim 1 , wherein the VOC comprises a first inverter (e.g., INV 1 ) comprising an input to receive the NVM output signal and to generate a first inverted signal at an output as the VOC output signal.
The memory circuit described above includes volatile output circuitry (VOC) comprising a first inverter (e.g., INV1). The inverter's input receives the NVM output signal, and its output generates an inverted signal as the VOC output signal. This inverter configuration provides a simple way to translate the voltage level from the NVM cell into a clear binary output.
3. The article of claim 1 , wherein the volatile output circuitry is an SRAM cell.
The memory circuit described above includes volatile output circuitry (VOC) implemented as an SRAM cell. This SRAM cell configuration allows the NVM cell to set the initial state of the SRAM, providing a way to store a non-volatile bit and then use it to configure a volatile memory element.
4. The article of claim 1 , wherein: the NVM cell is programmable to have a first programmed state by (i) turning off the first pass device and (ii) turning on the first select device to apply a programmable voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer of the first anti-fuse device; the NVM cell is programmable to have a second programmed state different from the first programmed state by (i) turning off the second pass device and (ii) turning on the second select device to apply a programmable voltage level across a gate oxide layer of the second anti-fuse device to create a permanent breakdown path through the gate oxide layer of the second anti-fuse device; and the volatile output circuitry is drivable using the NVM cell by (i) turning off the first and second select devices, (ii) applying read voltages to the first and second anti-fuse devices' gates, and (iii) turning on the first and second pass devices to pass a shorted voltage at the first and second nodes to the VOC input node.
In the memory circuit described above, the NVM cell is programmed in two ways. To program the first state, the first pass transistor is off, the first select transistor is on, and a programming voltage is applied to the first anti-fuse to permanently blow it. To program the second state, the second pass transistor is off, the second select transistor is on, and a programming voltage is applied to the second anti-fuse to permanently blow it. To read the programmed state, both select transistors are turned off, read voltages are applied to the anti-fuses, and both pass transistors are turned on, passing the resulting voltage to the volatile output circuitry (VOC).
5. The article of claim 4 , wherein the volatile output circuitry is drivable by: programming the NVM cell to have either the first or second programmed state; and then driving the volatile output circuitry using the NVM cell such that: if the NVM cell is programmed in the first programmed state, then the NVM output signal drives the volatile output circuitry based on the first programmed state; and if the NVM cell is programmed in the second programmed state, then the NVM output signal drives the volatile output circuitry based on the second programmed state.
The memory circuit from above uses the NVM to configure the volatile memory by first programming the NVM cell to a specific state (either blowing the first anti-fuse or the second), and then, using the resulting output of the NVM cell to drive the volatile output circuitry. Depending on whether the first or second anti-fuse is blown, the volatile output circuitry is driven to a different state, reflecting the programmed state of the NVM cell.
6. The article of claim 4 , wherein the NVM cell in operation implements a programmable voltage divider wherein in the first programmed state, the shorted voltage is on one side of a common-mode voltage for the NVM cell and in the second programmed state, the shorted voltage is on the other side of the common-mode voltage for the NVM cell.
In the memory circuit described above, the NVM cell functions as a programmable voltage divider during the read operation. When the first anti-fuse is blown, the resulting voltage at the VOC input is on one side of a common-mode voltage. Conversely, when the second anti-fuse is blown, the resulting voltage is on the other side of the common-mode voltage, allowing the VOC to easily differentiate between the two programmed states.
7. The article of claim 1 , wherein: the first and second select devices are controllable by a common program-enable control signal; and the first and second pass devices are controllable by a common transfer-enable control signal.
In the memory circuit described above, the first and second select transistors are controlled by a single program-enable signal, meaning they are turned on and off simultaneously during programming. Similarly, the first and second pass transistors are controlled by a single transfer-enable signal, meaning they are turned on and off simultaneously during the read operation.
8. The article of claim 1 , wherein: the first and second select devices are controllable by a common program-enable control signal; and the first and second pass devices are controllable by independent transfer-enable control signals.
In the memory circuit described above, the first and second select transistors are controlled by a single program-enable signal, meaning they are turned on and off simultaneously during programming. However, the first and second pass transistors are controlled by separate and independent transfer-enable signals, allowing for individual control during the read operation.
9. The article of claim 1 , wherein: the first and second select devices are controllable by independent program-enable control signals; and the first and second pass devices are controllable by a common transfer-enable control signal.
In the memory circuit described above, the first and second select transistors are controlled by independent program-enable signals, meaning they can be turned on and off independently during programming. However, the first and second pass transistors are controlled by a single transfer-enable signal, meaning they are turned on and off simultaneously during the read operation.
10. The article of claim 1 , wherein the memory circuit is part of an integrated circuit comprising multiple instances of the memory circuit distributed over the integrated circuit, wherein, for each instance of the memory circuit, the NVM cell is co-located with the volatile output circuitry.
The memory circuit from above is replicated multiple times on an integrated circuit. Each NVM cell is placed physically close to its associated volatile output circuitry (VOC), minimizing the distance between the non-volatile storage and the volatile output, improving performance and reducing area.
11. The article of claim 10 , wherein the integrated circuit is a field-programmable gate array.
The integrated circuit containing multiple instances of the memory circuit, where each NVM cell is co-located with the volatile output circuitry, is specifically a field-programmable gate array (FPGA). This arrangement is beneficial in FPGAs for configuring logic and routing resources using non-volatile memory elements adjacent to the configurable logic.
12. A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising: a first anti-fuse device; a second anti-fuse device; a first select device connected in series with the first anti-fuse device at a first node; a second select device connected in series with the second anti-fuse device at a second node; a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node; and a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by: turning off the first select device; applying a read voltage to the first anti-fuse device's gate; and turning on the first pass device to pass a voltage at the first node to the NVM output node, wherein: when the first anti-fuse device is blown, the voltage at the first node passed to the NVM output node will be at a first level; when the first anti-fuse device is not blown, the voltage at the first node passed to the NVM output node will be at a second level different from the first level; and turning off the first select device comprises turning off the first and the second select devices; applying a read voltage to the first anti-fuse device's gate comprises applying read voltages to the gates of the first and the second anti-fuse devices; and turning on the first pass device comprises turning on the first and the second pass devices to pass a shorted voltage at the first and second nodes to the NVM output node, wherein: if the first anti-fuse device is blown and the second anti-fuse device is not blown, the shorted voltage passed to the NVM output node will be at a first level; and if the first anti-fuse device is not blown and the second anti-fuse device is blown, the shorted voltage passed to the NVM output node will be at a second level different from the first level.
A method for reading a bit value from a programmable NVM cell, with two anti-fuses, each connected to a select and pass transistor, involves turning off both select transistors and applying read voltages to the gates of both anti-fuses. Turning on both pass transistors connects the anti-fuse outputs to the NVM output node. If the first anti-fuse is blown but the second is not, the voltage at the output is at a first level. If the second anti-fuse is blown but the first is not, the voltage is at a different second level.
13. The method of claim 12 , wherein the NVM cell functions as a programmable voltage divider such that: when the first anti-fuse device is blown and the second anti-fuse device is not blown, the shorted voltage is on one side of a common-mode voltage for the NVM cell and when the first anti-fuse device is not blown and the second anti-fuse device is blown, the shorted voltage is on the other side of the common-mode voltage for the NVM cell.
The method of reading from the NVM cell described above functions as a programmable voltage divider. If the first anti-fuse is blown and the second is not, the voltage at the output is on one side of a common-mode voltage. Conversely, if the second anti-fuse is blown and the first is not, the output voltage is on the other side of the common-mode voltage.
14. A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising: a first anti-fuse device; a second anti-fuse device; a first select device connected in series with the first anti-fuse device at a first node; a second select device connected in series with the second anti-fuse device at a second node; a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node; and a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by: turning off the first select device; applying a read voltage to the first anti-fuse device's gate; and turning on the first pass device to pass a voltage at the first node to the NVM output node, wherein: when the first anti-fuse device is blown, the voltage at the first node passed to the NVM output node will be at a first level; when the first anti-fuse device is not blown, the voltage at the first node passed to the NVM output node will be at a second level different from the first level; reading an other bit value from the NVM cell by: turning off the second select device; applying a read voltage to the second anti-fuse device's gate; and turning on the second pass device to pass a voltage at the second node to the NVM output node, wherein: if the second anti-fuse device is blown, then the voltage at the second node passed to the NVM output node will be at a third level; and if the second anti-fuse device is not blown, then the voltage at the second node passed to the NVM output node will be at a fourth level different from the third level.
A method for reading a bit value from a programmable NVM cell with two anti-fuses involves reading the state of each anti-fuse independently. To read the first bit, turn off the first select transistor, apply a read voltage to the first anti-fuse, and turn on the first pass transistor. The output voltage will be at one level if the anti-fuse is blown and another level if it is not. A second bit is read by turning off the second select transistor, applying a read voltage to the second anti-fuse, and turning on the second pass transistor. The resulting output will be at a different level depending on whether the second anti-fuse is blown.
15. A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising: a first anti-fuse device; a second anti-fuse device; a first select device connected in series with the first anti-fuse device at a first node; a second select device connected in series with the second anti-fuse device at a second node; a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node; and a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by: turning off the first select device; applying a read voltage to the first anti-fuse device's gate; and turning on the first pass device to pass a voltage at the first node to the NVM output node, wherein: when the first anti-fuse device is blown, the voltage at the first node passed to the NVM output node will be at a first level; when the first anti-fuse device is not blown, the voltage at the first node passed to the NVM output node will be at a second level different from the first level; and prior to reading the bit value from the NVM cell, programming the bit value into the NVM cell by: turning off the first pass device; and turning on the first select device to apply a programmable voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer of the first anti-fuse device.
A method for operating an NVM cell includes both programming and reading. To program a bit value, turn off the first pass transistor and turn on the first select transistor to apply a programming voltage across the first anti-fuse's gate oxide, permanently blowing it. To read the bit value, turn off the first select transistor, apply a read voltage to the first anti-fuse's gate, and turn on the first pass transistor. The output voltage will indicate whether the anti-fuse is blown or not.
16. The method of claim 14 , further comprising, prior to reading an other bit value from the NVM cell, programming the other bit value into the NVM cell by: turning off the second pass device; and turning on the second select device to apply a programmable voltage level across a gate oxide layer of the second anti-fuse device to create a permanent breakdown path through the gate oxide layer of the second anti-fuse device.
The method described above programs and reads another bit value in the NVM cell. First, program the bit by turning off the second pass transistor and turning on the second select transistor to apply a programming voltage across the second anti-fuse's gate oxide, permanently blowing it. The bit is read by turning off the second select transistor, applying a read voltage to the second anti-fuse's gate, and turning on the second pass transistor.
17. The method of claim 12 , further comprising controlling the first and second select devices by a common program-enable control signal and controlling the first and second pass devices by a common transfer-enable control signal.
The method for reading a bit value from a programmable NVM cell, with two anti-fuses, involves controlling the first and second select devices by a common program-enable control signal, such that they are enabled together during programming. The method also includes controlling the first and second pass devices by a common transfer-enable control signal, such that they are enabled together during a read operation.
18. The method of claim 12 , further comprising controlling the first and second select devices by a common program-enable control signal and controlling the first and second pass devices by separate and independent transfer-enable control signals.
The method for reading a bit value from a programmable NVM cell, with two anti-fuses, involves controlling the first and second select devices by a common program-enable control signal, such that they are enabled together during programming. The first and second pass devices are controlled independently allowing each anti-fuse's output to be read separately.
19. The method of claim 12 , further comprising controlling the first and second select devices are by independent program-enable control signals and controlling the first and second pass devices by a common transfer-enable control signal.
The method for reading a bit value from a programmable NVM cell, with two anti-fuses, involves controlling the first and second select devices are by independent program-enable control signals. The first and second pass devices are controlled by a common transfer-enable control signal.
20. An article of manufacture comprising a memory circuit comprising: a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device; a programmable volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell, wherein the first pass device is connected between the first node and the VM input node and usable to selectively pass a voltage at the first node to the VM input node, and control logic configured to (i) program the NVM cell by turning off the first pass device and turning on the first select device to apply a program voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer and to (ii) cause the VM cell to be configured by the programmed NVM cell by turning off the first select device, applying a read voltage to a gate of the first anti-fuse device, and turning on the first pass device to change the voltage at the VM input node using sufficient current flow through the gate oxide layer of the first anti-fuse device by an amount sufficient to flip the VM output signal.
A memory circuit comprises a non-volatile memory (NVM) cell and a volatile memory (VM) cell controlled by logic. The NVM cell consists of an anti-fuse, a select transistor, and a pass transistor. The pass transistor connects the NVM cell to the VM cell's input. The control logic programs the NVM by turning off the pass transistor and turning on the select transistor to blow the anti-fuse. After programming, the NVM cell configures the VM cell by turning off the select transistor, applying a read voltage to the anti-fuse, and turning on the pass transistor, passing enough current to flip the VM cell's output.
21. The article of claim 20 , wherein when the NVM cell is not programmed, (i) the first anti-fuse device is not blown, (ii) the NVM output signal is insufficiently definite for use in programming the VM cell, and (iii) the VM cell is programmable independent of the NVM output signal; and when the NVM cell is programmed, (i) the first anti-fuse device is blown and (ii) the NVM output signal is sufficiently definite for use in programming the VM cell.
In the memory circuit described above, when the NVM cell's anti-fuse is not blown, its output is not well-defined and cannot reliably program the VM cell, which can be programmed independently. However, after the NVM cell is programmed by blowing the anti-fuse, its output is well-defined and can reliably program the VM cell.
22. The article of claim 20 , wherein the VM cell is configurable by pre-programming the VM cell to have a first programmed state independent of the NVM output signal; and then configuring the VM cell using the NVM cell such that: if the NVM cell is not programmed, then the NVM output signal does not change the VM cell from the first programmed state; and if the NVM cell is programmed, then the NVM output signal does change the VM cell to a second programmed state different from the first programmed state.
The memory circuit from above allows the volatile memory (VM) cell to be configured. First, the VM cell is pre-programmed to a known state, independent of the NVM cell. Then, if the non-volatile memory (NVM) cell is not programmed (anti-fuse not blown), its output does not change the VM cell's state. If the NVM cell *is* programmed (anti-fuse blown), its output forces the VM cell to switch to a different state.
23. The article of claim 20 , wherein the memory circuit is part of an integrated circuit comprising multiple instances of the memory circuit distributed over the integrated circuit, wherein, for each instance of the memory circuit, the NVM cell is co-located with the VM cell.
The memory circuit with an NVM cell and VM cell described above is replicated multiple times on an integrated circuit. Each NVM cell is placed physically close to its associated VM cell, minimizing the distance between the non-volatile storage and the volatile memory, improving performance and reducing area.
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October 19, 2015
June 6, 2017
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