A memory device includes a first memory array comprising a first bit cell and a second bit cell that are configured to provide a first reference signal and a second reference signal, respectively; a second memory array comprising a third bit cell that is configured to store a first logical state; a reference signal provision (RSP) unit, coupled to the first memory array, and configured to short the first and second reference signals so as to provide an averaged reference signal; and a sensing amplifier, coupled between the RSP unit and the second memory array, and configured to use the averaged reference signal to read out the first logical state stored by the third bit cell.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory device, comprising: a first memory array comprising a first bit cell and a second bit cell that are configured to provide a first reference signal and a second reference signal, respectively; a second memory array comprising a third bit cell that is configured to store a first logical state; a reference signal provision (RSP) unit, coupled to the first memory array, and configured to short the first and second reference signals so as to provide an averaged reference signal; and a sensing amplifier, coupled between the RSP unit and the second memory array, and configured to use the averaged reference signal to read out the first logical state stored by the third bit cell.
A memory device has two memory arrays. The first array contains two bit cells that output reference signals. The second array contains a bit cell that stores data (a logical 1 or 0). A Reference Signal Provision (RSP) unit, connected to the first array, shorts the two reference signals to create an average reference signal. A sensing amplifier, connected between the RSP unit and the second array, uses this averaged reference signal to read the data stored in the data bit cell. This allows for differential sensing using single-ended memory cells.
2. The memory device of claim 1 , wherein the first reference signal is associated with a discharging rate, and the second reference signal is associated with a leakage rate.
In the memory device described in claim 1, one reference signal from the first memory array represents a discharging rate, while the other reference signal represents a leakage rate. These differing rates are used to create the averaged reference signal.
3. The memory device of claim 2 , wherein the averaged reference signal is associated with an intermediate rate that is valued between the discharging rate and the leakage rate.
In the memory device described in claim 2, where one reference signal represents a discharging rate and another a leakage rate, the resulting averaged reference signal from the RSP unit has an intermediate rate. This intermediate rate falls between the discharging rate and the leakage rate.
4. The memory device of claim 1 , wherein the first, second and third bit cells each includes a single-ended memory bit cell.
In the memory device described in claim 1, the bit cells in both the first and second memory arrays are single-ended memory bit cells. This means each bit cell uses a single wire to represent a logical state, unlike differential bit cells that use two wires.
5. The memory device of claim 1 , wherein the RSP unit includes a PMOS transistor.
In the memory device described in claim 1, the Reference Signal Provision (RSP) unit, which shorts the reference signals from the first memory array, is implemented using a PMOS transistor.
6. The memory device of claim 1 , wherein the sensing amplifier includes a differential sensing amplifier that is configured to receive differential input signals.
In the memory device described in claim 1, the sensing amplifier is a differential sensing amplifier. It's designed to receive differential input signals, which are voltage differences used to determine the logical state of the data bit cell, improving noise immunity.
7. The memory device of claim 1 , wherein the first logical state is either a logical 1 or a logical 0.
In the memory device described in claim 1, the data bit cell in the second memory array stores a logical state. This state can be either a logical 1 or a logical 0.
8. The memory device of claim 1 , wherein the second memory array further includes a fourth bit cell that is configured to store a second logical state complementary to the first logical state.
In the memory device described in claim 1, the second memory array contains not just one, but two bit cells. One bit cell stores a logical state (1 or 0), and the other bit cell stores the complementary logical state (0 or 1, respectively).
9. The memory device of claim 8 , wherein the sensing amplifier is configured to use the averaged reference signal to read out the second logical state stored by the fourth bit cell.
In the memory device described in claim 8, where the second memory array has two bit cells storing opposite logical states, the sensing amplifier uses the averaged reference signal to read the logical state of both bit cells. The averaged reference is used to accurately determine the value for both the original data and its compliment.
10. A memory device, comprising: a first memory array comprising a first plurality of bit cells disposed along a row of the first memory array, wherein each of the first plurality of bit cells along the row is configured to provide a reference signal; a second memory array comprising a second plurality of bit cells, wherein each of the second plurality of bit cells is configured to store a respective logical state; a reference signal provision (RSP) circuit, coupled to the first memory array, and configured to short the reference signals so as to provide a globally averaged reference signal; and a plurality of sensing amplifiers, coupled between the RSP circuit and the second memory array, and each configured to use the averaged reference signal to read out the respective logical state presented at each bit cell of the second memory array.
A memory device consists of two memory arrays. The first array has multiple bit cells arranged in a row, each outputting a reference signal. The second array has multiple bit cells, each storing data. A Reference Signal Provision (RSP) circuit, linked to the first array, shorts all reference signals to produce a single, globally averaged reference signal. Multiple sensing amplifiers, connected between the RSP circuit and the second array, use this averaged signal to read the data from each bit cell in the second array.
11. The memory device of claim 10 , wherein a first bit cell of the first plurality of bit cells of the first memory array is configured to provide a first reference signal associated with a discharging rate.
In the memory device described in claim 10, one bit cell in the first memory array (the array providing reference signals) outputs a reference signal that is associated with a discharging rate. This means the voltage level of this reference signal decreases at a certain rate.
12. The memory device of claim 11 , wherein a second bit cell of the first plurality of bit cells of the first memory array is configured to provide a second reference signal associated with a leakage rate.
In the memory device described in claim 11, building on the idea of a discharging rate in the first array, a different bit cell in the same array outputs a reference signal associated with a leakage rate. This signal's voltage changes due to leakage current, at a different rate than the discharging rate.
13. The memory device of claim 12 , wherein the averaged reference signal is associated with an intermediate rate that is an averaged value of the discharging rate and the leakage rate.
In the memory device described in claim 12, where the reference signals in the first array represent different rates, the globally averaged reference signal produced by the RSP circuit will have a rate that represents an average value between the discharging rate and the leakage rate of the reference signals.
14. The memory device of claim 10 , wherein the first and second pluralities of bit cells each includes a single-ended memory bit cell.
In the memory device described in claim 10, the bit cells in both the first and second memory arrays are single-ended memory bit cells. Each bit cell uses a single wire to represent a logical state, simplifying the design but potentially reducing noise immunity compared to differential bit cells.
15. The memory device of claim 10 , wherein the RSP circuit includes a plurality of PMOS transistors.
In the memory device described in claim 10, the Reference Signal Provision (RSP) circuit, responsible for shorting the reference signals from the first memory array to create the averaged signal, is implemented using multiple PMOS transistors.
16. The memory device of claim 15 , wherein at least a first PMOS transistor is coupled to a first pair of adjacent bit cells of the first plurality of bit cells, a second PMOS transistor is coupled to a second pair of adjacent bit cells of the first plurality of bit cells, and a third PMOS transistor is coupled to the first and second PMOS transistors.
In the memory device described in claim 15, which uses PMOS transistors in the RSP circuit, a first PMOS transistor shorts the reference signals from a first pair of adjacent bit cells in the first array. A second PMOS transistor shorts the reference signals from a second pair of adjacent bit cells. A third PMOS transistor connects the first and second PMOS transistors.
17. The memory device of claim 16 , wherein the first PMOS transistor is configured to short reference signals respectively provided by the first pair of adjacent bit cells so as to provide a first averaged reference signal, the second PMOS transistor is configured to short reference signals respectively provided by the second pair of adjacent bit cells so as to provide a second averaged reference signal, and the third PMOS transistor is configure to short the first and second averaged reference signals so as to provide the globally averaged reference signal.
Expanding on claim 16, the first PMOS transistor shorts reference signals from a first pair of adjacent bit cells to generate a first averaged reference signal. The second PMOS transistor similarly creates a second averaged reference signal from a second pair. Then, the third PMOS transistor shorts these *averaged* signals together to create the final globally averaged reference signal used by the sensing amplifiers.
18. The memory device of claim 17 , wherein the reference signals provided by the first pair of adjacent bit cells include a first discharging rate and a first leakage rate, respectively, the reference signals provided by the second pair of adjacent bit cells include a second discharging rate and a second leakage rate, respectively, and wherein the first discharging rate is different from the second discharging rate and the first leakage rate is different from the second leakage rate.
In the memory device described in claim 17, the reference signals from the bit cells connected by the PMOS transistors have varying rates. The first pair has a first discharging rate and a first leakage rate, while the second pair has a second discharging rate and a second leakage rate. The discharging and leakage rates between the pairs are different, ensuring a more robust averaged reference signal.
19. A memory device, comprising: a first memory array comprising a first bit cell and a second bit cell that are configured to provide a first reference signal with a discharging rate and a second reference signal with a leakage rate, respectively, when the first and second bit cells are being accessed; a second memory array comprising a third bit cell that is configured to store a first logical state; a reference signal provision (RSP) unit, coupled to the first memory array, and is configured to short the first and second reference signals so as to provide an averaged reference signal with an intermediate discharging rate that is valued between the discharging rate and the leakage rate; and a differential sensing amplifier, coupled between the RSP unit and the second memory array, and configured to use the intermediate discharging rate to read out the first logical state presented at the third bit cell.
A memory device uses two memory arrays. The first has two bit cells providing reference signals: one discharging rapidly, the other leaking slowly. A Reference Signal Provision (RSP) unit shorts these signals to create an averaged signal with an intermediate discharge rate. The second array stores data. A differential sensing amplifier uses the averaged signal to read data from the second array, using the intermediate rate for comparison.
20. The memory device of claim 19 , wherein the RSP unit include a PMOS transistor.
In the memory device described in claim 19, the Reference Signal Provision (RSP) unit, which averages the reference signals with differing discharge rates, is implemented using a PMOS transistor.
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October 7, 2016
June 13, 2017
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