Aspects of a continuous-time memory cell circuit are described. In various embodiments, the memory cell circuit may comprise a memory cell, a current source coupled to the memory cell, and circuitry for programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop between a gate terminal of the memory cell and a reference control input. Based on the circuitry for programming, the memory cell may be programmed according to various voltage and/or current references, by linear injection and/or tunneling mechanisms. According to various aspects, the circuitry for programming drives a memory cell to converge to a voltage target for programming within a short period of time and to a suitable level of accuracy.
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1. A method, comprising: providing, via a current source, channel current for a memory cell having a source terminal, a drain terminal, and a gate terminal, wherein the current source is coupled to the source terminal or the drain terminal of the memory cell; and continuously programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop to monitor the gate terminal of the memory cell and continuously adapting at least one of an amount of current that is supplied by the current source or the drain-to-source voltage of the memory cell set by a linearizing amplifier, wherein the linearizing amplifier sets a drain-to-source voltage of the memory cell using the feedback loop, from the source terminal or drain terminal of the memory cell, to the gate terminal of the memory cell, wherein the current source comprises a current mirror, circuitry for programming comprises an operational transconductance amplifier (OTA) having an output and a pair of differential inputs, the current mirror is coupled to the source terminal of the memory cell, the output of the OTA is coupled to a reference control input of the current mirror, and the differential inputs of the OTA are coupled to the gate of the memory cell and the target voltage for programming.
A method for programming a floating gate memory cell involves using a current source to supply channel current to the memory cell, which has a source, drain, and gate. The current source connects to either the source or drain. The memory cell is continuously programmed at a rate that adapts based on a target voltage. A feedback loop monitors the gate voltage and adjusts either the current source's output or the drain-to-source voltage, which is controlled by a linearizing amplifier. The amplifier sets the drain-to-source voltage using feedback from the source or drain to the gate. Specifically, a current mirror is used as the current source, connecting to the memory cell's source. An operational transconductance amplifier (OTA) controls the current mirror, with the OTA's output connected to the current mirror's reference input. The OTA's inputs are connected to the memory cell's gate and the target programming voltage.
2. A method, comprising: providing, via a current source, channel current for a memory cell having a source terminal, a drain terminal, and a gate terminal, wherein the current source is coupled to the source terminal or the drain terminal of the memory cell; and continuously programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop to monitor the gate terminal of the memory cell and continuously adapting at least one of an amount of current that is supplied by the current source or the drain-to-source voltage of the memory cell set by a linearizing amplifier, wherein the linearizing amplifier sets a drain-to-source voltage of the memory cell using the feedback loop, from the source terminal or drain terminal of the memory cell, to the gate terminal of the memory cell, wherein circuitry for programming comprises a differential amplifier having a pair of differential inputs and a diode-connected transistor load, wherein one input of the pair of differential inputs is coupled to the gate terminal of the memory cell, another input of the pair of differential inputs is coupled to the target voltage for programming, and an output of the differential amplifier is coupled to an input of the linearizing amplifier such that the drain-to-source voltage of the memory cell is adjusted during programming to adapt the program rate.
This invention relates to adaptive programming of memory cells, particularly for controlling the programming rate of a memory cell using a feedback loop. The method involves providing a channel current to a memory cell through a current source connected to either the source or drain terminal. The memory cell is programmed at an adaptive rate based on a target voltage, with the feedback loop continuously monitoring the gate terminal to adjust either the current supplied by the source or the drain-to-source voltage of the memory cell. A linearizing amplifier sets the drain-to-source voltage, which is derived from the source or drain terminal to the gate terminal, ensuring precise control over the programming process. The programming circuitry includes a differential amplifier with differential inputs and a diode-connected transistor load. One input of the differential amplifier is connected to the memory cell's gate terminal, while the other input receives the target programming voltage. The differential amplifier's output is fed into the linearizing amplifier, which adjusts the drain-to-source voltage during programming to dynamically adapt the programming rate. This approach ensures accurate and efficient programming by continuously monitoring and adjusting the memory cell's operating conditions.
3. A method, comprising: providing, via a current source, channel current for a memory cell having a source terminal, a drain terminal, and a gate terminal, wherein the current source is coupled to the source terminal or the drain terminal of the memory cell; and continuously programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop to monitor the gate terminal of the memory cell and continuously adapting at least one of an amount of current that is supplied by the current source or the drain-to-source voltage of the memory cell set by a linearizing amplifier, wherein the linearizing amplifier sets a drain-to-source voltage of the memory cell using the feedback loop, from the source terminal or drain terminal of the memory cell, to the gate terminal of the memory cell, wherein the current source is coupled to the source terminal of the memory cell, and a negative voltage generator is coupled to the drain terminal of the memory cell.
A method for programming a floating gate memory cell involves using a current source to supply channel current to the memory cell, which has a source, drain, and gate. The current source connects to either the source or drain. The memory cell is continuously programmed at a rate that adapts based on a target voltage. A feedback loop monitors the gate voltage and adjusts either the current source's output or the drain-to-source voltage, which is controlled by a linearizing amplifier. The amplifier sets the drain-to-source voltage using feedback from the source or drain to the gate. Specifically, the current source is connected to the memory cell's source terminal, and a negative voltage generator is connected to the drain terminal of the memory cell.
4. The method of claim 3 , wherein the negative voltage generator comprises an operational transconductance amplifier (OTA), a capacitor, and at least two switches switched by complementary phases of a clock signal.
The method of programming a floating gate memory cell using a current source, continuous adaptive programming, a feedback loop, and a linearizing amplifier, with a negative voltage generator connected to the drain terminal of the memory cell, now specifies that the negative voltage generator comprises an operational transconductance amplifier (OTA), a capacitor, and at least two switches. These switches are controlled by complementary phases of a clock signal to generate the negative voltage.
5. A method, comprising: providing current, via a first current source coupled to a source terminal of a memory cell having the source terminal, a drain terminal, and a gate terminal; providing current, via a second current source coupled to the gate terminal of the memory cell; and continuously programming the memory cell at adaptive rate, based on a target voltage for programming, using a feedback loop between the gate terminal of the memory cell and either the first current source, the second current source, or a source terminal of a bias transistor with: a drain terminal of the bias transistor coupled to the gate terminal of the memory cell, a gate terminal of the bias transistor coupled to the source terminal of the memory cell, and the source terminal of the bias transistor coupled to a bias voltage.
A method for programming a floating gate memory cell uses two current sources. A first current source supplies current to the memory cell's source terminal. A second current source supplies current to the memory cell's gate terminal. The memory cell is continuously programmed at a rate that adapts based on a target voltage. A feedback loop exists between the memory cell's gate and either the first current source, the second current source, or the source terminal of a bias transistor. This bias transistor has its drain connected to the memory cell's gate, its gate connected to the memory cell's source, and its source connected to a bias voltage.
6. The method of claim 5 , wherein the first current source comprises a current mirror, the circuitry for programming comprises an operational transconductance amplifier (OTA), and an output of the OTA is coupled to a reference control input of the current mirror.
The method of programming a floating gate memory cell using two current sources and a bias transistor, where programming adapts based on a target voltage using feedback, now specifies that the first current source (connected to the source terminal) is a current mirror. The programming circuitry includes an operational transconductance amplifier (OTA), and the OTA's output is connected to a reference control input of the current mirror, adjusting the current supplied to the source terminal based on the feedback.
7. The memory cell circuit of claim 5 , wherein the second current source comprises a current mirror; the circuitry for programming comprises an operational transconductance amplifier (OTA), and an output of the OTA is coupled to a reference control input of the current mirror.
The memory cell circuit uses two current sources and a bias transistor, where programming adapts based on a target voltage using feedback, now specifies that the second current source (connected to the gate terminal) is a current mirror. The programming circuitry includes an operational transconductance amplifier (OTA), and the OTA's output is connected to a reference control input of the current mirror, adjusting the current supplied to the gate terminal based on the feedback.
8. The method of claim 5 , wherein circuitry for programming comprises a differential amplifier having a pair of differential inputs and a diode-connected transistor load, wherein one input of the pair of differential inputs is coupled to the gate terminal of the memory cell; the other input of the differential inputs is coupled to the target voltage for programming; and an output of the differential amplifier is coupled to the source terminal of the bias transistor such that the source terminal of the memory is continuously adjusted during programming to adapt the program rate.
The method of programming a floating gate memory cell using two current sources and a bias transistor, where programming adapts based on a target voltage using feedback, now specifies that the programming circuitry includes a differential amplifier with differential inputs and a diode-connected transistor load. One input of the differential amplifier is connected to the memory cell's gate, and the other input is connected to the target programming voltage. The amplifier's output is connected to the source terminal of the bias transistor, which continuously adjusts the source terminal of the memory cell to adapt the programming rate.
9. The method of claim 5 , wherein a negative voltage generator is coupled to the drain terminal of the memory cell.
The method of programming a floating gate memory cell using two current sources and a bias transistor, where programming adapts based on a target voltage using feedback, now specifies that a negative voltage generator is connected to the drain terminal of the memory cell.
10. The method of claim 9 , wherein the negative voltage generator comprises an operational transconductance amplifier (OTA), a capacitor, and at least two switches switched by complementary phases of a clock signal.
The method of programming a floating gate memory cell using two current sources, a bias transistor, and a negative voltage generator connected to the drain terminal of the memory cell, where programming adapts based on a target voltage using feedback, now specifies that the negative voltage generator comprises an operational transconductance amplifier (OTA), a capacitor, and at least two switches. These switches are controlled by complementary phases of a clock signal to generate the negative voltage.
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November 13, 2015
June 13, 2017
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