A computer system for controlling access to a shared data structure includes a shared memory coupled to first and second processing units that stores a multi-lock to control access to a shared data structure. The multi-lock includes a first sub-lock associated with the first processing unit and a second sub-lock associated with the second processing unit The system also includes a data access control engine to receive a request to read from the data structure from the first processing unit and, as a result, determine whether a privately modifiable copy the first sub-lock exists in a first cache dedicated to the first processing unit, acquire a read portion of the first sub-lock and not communicate the acquisition across a coherence bus if a privately modifiable copy of the first sub-lock exists in the first cache, and if a privately modifiable copy of the first sub-lock does not exist in the first cache, load the first sub-lock into the first cache if no copy is in the first cache, shootdown other copies of the first sub-lock, and acquire the read portion of the first sub-lock.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer system for controlling access to a shared data structure, comprising: a first processing unit coupled to a first cache dedicated to the first processing unit; a second processing unit coupled to a second cache dedicated to the second processing unit; a shared memory coupled to the first and second processing units that stores a multi-lock to control access to a data structure shared by the first and second processing units, the multi-lock comprising a first sub-lock associated with the first processing unit and a second sub-lock associated with the second processing unit, the sub-locks comprising a read portion and a write portion; a coherence bus that couples the first and second caches and carries coherency information between the first and second caches; and a data access control engine to receive a request to read from the data structure from the first processing unit and, as a result: determine whether a privately modifiable copy the first sub-lock exists in the first cache; acquire the read portion of the first sub-lock and not communicate the acquisition across the coherence bus if a privately modifiable copy of the first sub-lock exists in the first cache: and if a privately modifiable copy of the first sub-lock does not exist in the first cache, load the first sub-lock into the first cache if no copy is in the first cache, shootdown other copies of the first sub-lock, and acquire the read portion of the first sub-lock.
A computer system controls access to shared data using a multi-lock. Two processors, each with a dedicated cache, share memory containing the data and the multi-lock. The multi-lock has sub-locks, one per processor, each with read and write portions. A coherence bus ensures cache consistency. When the first processor requests to read data, the system checks if it has a "privately modifiable" copy of its sub-lock in its cache. If so, it acquires the read portion locally, without bus communication. Otherwise, it loads the sub-lock into its cache (if not already present), invalidates other cached copies ("shootdown"), and then acquires the read portion. This allows fast, local read access when possible, minimizing bus traffic.
2. The computer system of claim 1 wherein the coherence bus carries coherency information that implements a MESI cache coherence protocol.
The computer system described for controlling shared data access, using a multi-lock with sub-locks per processor and local caches, uses a coherence bus that specifically implements the MESI (Modified, Exclusive, Shared, Invalid) cache coherence protocol. The MESI protocol manages the states of cached data to ensure consistency between the processor caches and main memory. The system leverages MESI for coherency information exchange during lock acquisition and release operations related to the sub-locks.
3. The computer system of claim 2 wherein a copy of the first sub-lock is privately modifiable if a cache line that stores the first sub-lock in the first cache is in a modified or exclusive state.
In the computer system that manages shared data access with a multi-lock and uses a MESI cache coherence protocol, a sub-lock copy in a processor's cache is "privately modifiable" if the cache line storing that sub-lock is in either the "Modified" or "Exclusive" state according to the MESI protocol. This means the processor has the only valid copy, potentially with unsaved changes. A processor can directly acquire the read portion of its sub-lock from its cache without external communication when the state is Modified or Exclusive.
4. The computer system of claim 2 wherein a copy of the first sub-lock is not privately modifiable if a cache line that stores the first sub-lock in the first cache is in a shared or invalid state or there is no cache line that stores the first sub-lock in the first cache, and wherein if the cache line that stores the first sub-lock in the first cache is in the shared state, a shootdown is issued to the second cache over the coherence bus and the read portion of the first sub-lock is acquired.
In the computer system that manages shared data access with a multi-lock and uses a MESI cache coherence protocol, a sub-lock copy in a processor's cache is not "privately modifiable" if the cache line storing it is in the "Shared" or "Invalid" state, or if the sub-lock isn't in the cache at all. Specifically, if the sub-lock is in the "Shared" state (meaning other caches might have a copy), a "shootdown" signal is sent over the coherence bus to invalidate those other copies (e.g., to the second cache). After the shootdown completes, the read portion of the sub-lock can be acquired.
5. The computer system of claim 2 wherein the data access control engine is further configured to receive a request to write to the shared data structure from the first processing unit and, as a result, for each sub-lock of the multi-lock: acquire the write portion of the sub-lock if the read portion indicates there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a modified or exclusive state; acquire the write portion of the sub-lock and issue a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a shared state; and if a privately modifiable copy of the sub-lock does not exist in the first cache, load the sub-lock into the first cache if no copy is in the first cache, acquire the write portion of the sub-lock, and issue a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock.
The computer system controlling shared data access with a multi-lock is extended to handle write requests. When a processor wants to write, it tries to acquire the write portion of each sub-lock. It acquires the write portion locally only if no other processor holds a read lock and the sub-lock is in a modified/exclusive state in the local cache. If no other processor holds a read lock and the sub-lock is in a shared state, it acquires the write portion and sends a "shootdown" to other caches. If the sub-lock isn't privately modifiable, it's loaded into the cache (if not present), the write portion acquired, and a "shootdown" sent to other caches if no other processor holds a read lock.
6. The computer system of claim 1 wherein a shootdown is issued to the second cache over the coherence bus when the first sub-lock is loaded into the first cache from the shared memory.
In the computer system described, for controlling access to shared data using a multi-lock with sub-locks per processor and local caches, when a processor loads its sub-lock into its cache from shared memory (because it wasn't already present), a "shootdown" signal is immediately sent over the coherence bus to the other processor's cache. This ensures that any potentially stale copies of the sub-lock in other caches are invalidated before the loading processor uses the sub-lock.
7. A method for controlling access to a shared data structure, comprising: storing a multi-lock to control access to the data structure, the multi-lock comprising a first sub-lock associated with a first processing unit and a second sub-lock associated with a second processing unit, each sub-lock comprising a read portion and a write portion; receiving a request to read from the data structure from the first processing unit; determining whether a privately modifiable copy of the first sub-lock exists in a first cache dedicated to the first processing unit; acquiring the read portion of the first sub-lock and not communicating the acquisition across a coherence bus between the first cache and a second cache dedicated to the second processing unit if a privately modifiable copy of the first sub-lock exists in the first cache; and loading the first sub-lock into the first cache if no copy is in the first cache and acquiring the read portion of the first sub-lock if a privately modifiable copy of the first sub-lock does not exist in the first cache.
A method controls access to shared data using a multi-lock. A multi-lock, containing sub-locks for each processor, is stored. Each sub-lock has read and write portions. When a processor requests to read data, the method checks if it has a "privately modifiable" copy of its sub-lock in its local cache. If yes, it acquires the read portion locally, without bus communication. If no, it loads the sub-lock into the cache (if not present) and acquires the read portion. This prioritizes fast, local reads and reduces bus traffic.
8. The method of claim 7 wherein the coherence bus carries coherency information that implements a MESI cache coherence protocol.
The method for controlling shared data access, using a multi-lock with sub-locks per processor and local caches, relies on a coherence bus implementing the MESI (Modified, Exclusive, Shared, Invalid) cache coherence protocol. The MESI protocol ensures that all caches have consistent views of the shared data and lock status.
9. The method of claim 8 wherein a copy of the first sub-lock is privately modifiable if a cache line that stores the first sub-lock in the first cache is in a modified or exclusive state.
The method using a multi-lock and MESI cache coherence defines that a sub-lock copy is "privately modifiable" if the corresponding cache line is in the "Modified" or "Exclusive" state. This means the processor owns the only valid copy and can safely acquire the read portion without external communication.
10. The method of claim 8 wherein a copy of the first sub-lock is not privately modifiable if a cache line that stores the first sub-lock in the first cache is in a shared or invalid state or there is no cache line that stores the first sub-lock in the first cache, and wherein if the cache line that stores the first sub-lock in the first cache is in the shared state, the method further comprises issuing a shootdown to the second cache over the coherence bus and acquiring the read portion of the first sub-lock.
The method for controlling shared data access specifies that a sub-lock is not "privately modifiable" if its cache line is "Shared", "Invalid", or not present. If the state is "Shared", a "shootdown" signal is sent to invalidate copies in other caches, after which the read portion can be acquired.
11. The method of claim 8 further comprising receiving a request to write to the data structure from the first processing unit and, as a result, for each sub-lock of the multi-lock: acquiring the write portion of the sub-lock if the read portion indicates there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a modified or exclusive state; acquiring the write portion of the sub-lock and issuing a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a shared state; and if a privately modifiable copy of the sub-lock does not exist in the first cache, loading the sub-lock into the first cache if no copy is in the first cache, acquiring the write portion of the sub-lock, and issuing a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock.
The method described for shared data access is extended to handle write requests. It acquires the write portion of a sub-lock locally if no other processors have a read lock and the cache line is modified/exclusive. If the cache line is shared and no other processor has a read lock, it acquires the write portion and sends a shootdown. Otherwise, it loads the sub-lock (if needed), acquires the write portion, and sends a shootdown (again only if no other processor has a read lock).
12. The method of claim 7 further comprising issuing a shootdown to the second cache over the coherence bus when the first sub-lock is loaded into the first cache from the shared memory.
In the shared data access control method, when a sub-lock is loaded from shared memory into a processor's cache, a "shootdown" is immediately sent over the coherence bus to invalidate potential stale copies in other caches.
13. A non-transitory computer-readable storage device storing software that, when executed by a processor including a coherence bus, causes the processor to: store a multi-lock to control access to a data structure, the multi-lock comprising a first sub-lock associated with a first processing unit and a second sub-lock associated with a second processing unit, each sub-lock comprising a read portion and a write portion: receive a request to read from the data structure from the first processing unit; determine whether a privately modifiable copy of the first sub-lock exists in a first cache dedicated to the first processing unit; acquire the read portion of the first sub-lock and not communicate the acquisition to a second cache dedicated to the second processing unit if a privately modifiable copy of the first sub-lock exists in the first cache; and load the first sub-lock into the first cache if no copy is in the first cache and acquire the read portion of the first sub-lock if a privately modifiable copy of the first sub-lock does not exist in the first cache.
A non-transitory storage device holds software to control data access using a multi-lock. When executed, the software stores a multi-lock with sub-locks per processor. Upon a read request, it checks for a "privately modifiable" sub-lock in the local cache. If found, it acquires the read portion locally. Otherwise, it loads the sub-lock (if needed) and acquires the read portion. The program minimizes communication overhead.
14. The non-transitory computer-readable storage device of claim 13 wherein the coherence bus carries coherency information that implements a MESI cache coherence protocol.
The software on the non-transitory storage medium utilizes a coherence bus with MESI protocol for consistent cache management while controlling access to the shared data. The MESI protocol ensures data integrity between caches.
15. The non-transitory computer-readable storage device of claim 14 wherein the processor receives a request to write to the data structure from the first processing unit and, as a result : for each sub-lock of the multi-lock: acquires the write portion of the sub-lock if the read portion indicates there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a modified or exclusive state; acquires the write portion of the sub-lock and issues a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock and a cache line storing the sub-lock in the first cache is in a shared state; and if a privately modifiable copy of the sub-lock does not exist in the first cache, loads the sub-lock into the first cache if no copy is in the first cache, acquires the write portion of the sub-lock, and issues a shootdown to caches other than the first cache if the read portion indicates that there are no processing units that have acquired the read portion of the sub-lock.
The software described further handles write requests. For each sub-lock, it acquires the write portion locally if no other processor has a read lock and the cache line is modified/exclusive. If the cache line is shared and no other processor has a read lock, it acquires the write portion and sends a shootdown. Otherwise, it loads the sub-lock (if needed), acquires the write portion, and sends a shootdown (again, if no other processor has a read lock).
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July 31, 2012
June 27, 2017
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